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preliminary information amd-k6?- iii e+ embedded processor data sheet publication # 23543 rev: a amendment/ 0 issue date: september 2000
trademarks amd, the amd logo, k6, 3dnow!, and combinations thereof, amd powernow!, e86, and super7 are trademarks, fusione86 is a service mark, and amd-k6 and risc86 are registered trademarks of advanced micro devices, inc. microsoft, windows, and windows nt are registered trademarks of microsoft corporation. netware is a registered trademark of novell, inc. mmx is a trademark of intel corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. the tap state diagram is reprinted from ieee std 1149.1-1990 ieee standard test access port and boundary-scan architecture, copyright ? 1990 by the institute of electrical and electronics engineers, inc. the ieee disclaims any responsibility or liability resulting from the placement and use in the described manner. information is reprinted with the permission of the ieee. ? 2000 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (amd) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
iii 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information if you have questions, were here to help you. the amd customer service network includes u.s. offices, international offices, and a customer training center. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff to answer e86? family hardware and software development questions. frequently accessed numbers are listed below. additional contact information is listed on the back of this manual. amds www site lists the latest phone numbers. technical support answers to technical questions are available online, through e-mail, and by telephone. go to amds home page at www.amd.com and follow the support link for the latest amd technical support phone numbers, software, and frequently asked questions. for technical support questions on all e86 embedded products, send e-mail to epd.support@amd.com (in the us and canada) or euro.tech@amd.com (in europe and the uk). you can also call the amd corporate applications hotline at: (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline www support for specific information on e86 products, access the amd home page at www.amd.com and follow the embedded processors link. these pages provide information on upcoming product releases, overviews of existing products, information on product support and tools, and a list of technical documentation. support tools include online benchmarking tools and codekit softwaretested source code example applications. many of the technical documents are available online in pdf form. questions, requests, and input concerning amds www pages can be sent via e-mail to web.feedback@amd.com . documentation and literature support data books, users manuals, data sheets, application notes, and product cds are free with a simple phone call. internationally, contact your local amd sales office for product literature.
iv amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information to order literature: web: www.amd.com/support/literature.html u.s. and canada: (800) 222-9323 third-party support amd fusione86 sm program partners provide an array of products designed to meet critical time-to-market needs. products and solutions available include chipsets, emulators, hardware and software debuggers, board-level products, and software development tools, among others. the www site and the e86? family products development tools cd, order #21058, describe these solutions. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
contents v 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii about this data sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix 1 amd-k6?-iiie+ embedded processor ..................................... 1 1.1 amd-k6?-iiie+ embedded processor features . . . . . . . . . . 3 1.2 process technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 super7? platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 internal architecture ................................................................ 11 2.1 microarchitecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 cache, instruction prefetch, and predecode bits . . . . . . . . . 16 2.3 instruction fetch and decode . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6 branch-prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 software environment ............................................................... 27 3.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . . . 44 3.3 memory management registers . . . . . . . . . . . . . . . . . . . . . . . 54 3.4 paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.5 descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.6 exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.7 instructions supported by the amd-k6?-iiie+ processor . 63 4 logic symbol diagram ............................................................... 91 5 signal descriptions .................................................................... 93 5.1 signal terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.2 a20m# (address bit 20 mask) . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3 a[31:3] (address bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.4 ads# (address strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.5 adsc# (address strobe copy) . . . . . . . . . . . . . . . . . . . . . . . . 96 5.6 ahold (address hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.7 ap (address parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.8 apchk# (address parity check) . . . . . . . . . . . . . . . . . . . . . . 99 5.9 be[7:0]# (byte enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.10 bf[2:0] (bus frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.11 boff# (backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.12 brdy# (burst ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.13 brdyc# (burst ready copy) . . . . . . . . . . . . . . . . . . . . . . . . 104 5.14 breq (bus request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.15 cache# (cacheable access) . . . . . . . . . . . . . . . . . . . . . . . . 105 5.16 clk (clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.17 d/c# (data/code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.18 d[63:0] (data bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
vi contents amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.19 dp[7:0] (data parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.20 eads# (external address strobe) . . . . . . . . . . . . . . . . . . . . 109 5.21 ewbe# (external write buffer empty) . . . . . . . . . . . . . . . . 110 5.22 ferr# (floating-point error) . . . . . . . . . . . . . . . . . . . . . . . 111 5.23 flush# (cache flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5.24 hit# (inquire cycle hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.25 hitm# (inquire cycle hit to modified line) . . . . . . . . . . . 113 5.26 hlda (hold acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.27 hold (bus hold request) . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.28 ignne# (ignore numeric exception) . . . . . . . . . . . . . . . . . 116 5.29 init (initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.30 intr (maskable interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.31 inv (invalidation request) . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5.32 ken# (cache enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.33 lock# (bus lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.34 m/io# (memory or i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.35 na# (next address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.36 nmi (non-maskable interrupt) . . . . . . . . . . . . . . . . . . . . . . . 123 5.37 pcd (page cache disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.38 pchk# (parity check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 5.39 pwt (page writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.40 reset (reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.41 rsvd (reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.42 scyc (split cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.43 smi# (system management interrupt) . . . . . . . . . . . . . . . . 130 5.44 smiact# (system management interrupt active) . . . . . . 131 5.45 stpclk# (stop clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.46 tck (test clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.47 tdi (test data input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.48 tdo (test data output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.49 tms (test mode select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.50 trst# (test reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.51 vcc2det (vcc2 detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.52 vcc2h/l# (vcc2 high/low) . . . . . . . . . . . . . . . . . . . . . . . . 136 5.53 vid[4:0] (voltage identification) . . . . . . . . . . . . . . . . . . . . . 137 5.54 w/r# (write/read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.55 wb/wt# (writeback or writethrough) . . . . . . . . . . . . . . . . 139 5.56 pin tables by type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.57 bus cycle definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6 amd powernow!? technology ............................................. 143 6.1 enhanced power management features . . . . . . . . . . . . . . . 143 6.2 dynamic core frequency and core voltage control . . . . . 150 7 bus cycles ................................................................................. 153 7.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.2 bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.3 memory reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.4 i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
contents vii 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 7.5 inquire and bus arbitration cycles . . . . . . . . . . . . . . . . . . . 168 7.6 special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 8 power-on configuration and initialization ............................ 199 8.1 signals sampled during the falling transition of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 8.2 reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 8.3 state of processor after reset . . . . . . . . . . . . . . . . . . . . . . 200 8.4 state of processor after init . . . . . . . . . . . . . . . . . . . . . . . . 203 9 cache organization .................................................................. 205 9.1 mesi states in the l1 data cache and l2 cache . . . . . . . . 207 9.2 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 9.3 cache operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 9.4 cache disabling and flushing . . . . . . . . . . . . . . . . . . . . . . . 211 9.5 l2 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 9.6 cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 9.7 cache-line replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 9.8 write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 9.9 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9.10 cache states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 9.11 cache coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 9.12 writethrough and writeback coherency states . . . . . . . . . 227 9.13 a20m# masking of cache accesses . . . . . . . . . . . . . . . . . . . 227 10 write merge buffer ................................................................. 229 10.1 ewbe# control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 10.2 memory type range registers . . . . . . . . . . . . . . . . . . . . . . . 231 10.3 memory-range restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 233 10.4 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 11 floating-point and multimedia execution units .................. 237 11.1 floating-point execution unit . . . . . . . . . . . . . . . . . . . . . . . 237 11.2 multimedia and 3dnow!? execution units . . . . . . . . . . . . 239 11.3 floating-point and mmx?/3dnow!? instruction compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 12 system management mode (smm) ........................................ 241 12.1 smm operating mode and default register values . . . . . 241 12.2 smm state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12.3 smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 12.4 smm base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 12.5 halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 12.6 i/o trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 12.7 i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 12.8 exceptions, interrupts, and debug in smm . . . . . . . . . . . . 250 13 test and debug ......................................................................... 251 13.1 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 13.2 three-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 13.3 boundary-scan test access port (tap) . . . . . . . . . . . . . . . . 253
viii contents amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 13.4 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 13.5 l2 cache and tag array testing . . . . . . . . . . . . . . . . . . . . . 264 13.6 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 14 clock control ............................................................................ 277 14.1 clock control states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 14.2 halt state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 14.3 stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 14.4 stop grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.5 epm stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 14.6 stop clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 15 electrical data .......................................................................... 287 15.1 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 15.2 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 15.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 15.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 15.5 power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16 signal switching characteristics ............................................ 297 16.1 clk switching characteristics . . . . . . . . . . . . . . . . . . . . . . . 298 16.2 clock switching characteristics for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.3 clock switching characteristics for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.4 valid delay, float, setup, and hold timings . . . . . . . . . . . 300 16.5 output delay timings for 100-mhz bus operation . . . . . . 300 16.6 input setup and hold timings for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.7 output delay timings for 66-mhz bus operation . . . . . . . 304 16.8 input setup and hold timings for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 16.9 reset and test signal timing . . . . . . . . . . . . . . . . . . . . . . 308 16.10 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 17 thermal design ........................................................................ 315 17.1 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . 315 17.2 measuring case temperature . . . . . . . . . . . . . . . . . . . . . . . . 319 17.3 layout and airflow considerations . . . . . . . . . . . . . . . . . . . 319 18 pin designations ....................................................................... 323 18.1 pins designations for cpga package . . . . . . . . . . . . . . . . . 324 18.2 pins designations for obga package . . . . . . . . . . . . . . . . . 328 19 package specifications ............................................................ 333 19.1 321-pin staggered cpga package specification . . . . . . . . 333 19.2 349-ball obga package specification . . . . . . . . . . . . . . . . . 334 20 ordering information .............................................................. 335 index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
list of figures ix 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information list of figures figure 1. amd-k6?-iiie+ processor block diagram . . . . . . . . . . . . . . . . 13 figure 2. cache sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. the instruction buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4. amd-k6?-iiie+ processor decode logic . . . . . . . . . . . . . . . . . 19 figure 5. amd-k6?-iiie+ processor scheduler . . . . . . . . . . . . . . . . . . . . 22 figure 6. register x and y pipeline functional units . . . . . . . . . . . . . . . 24 figure 7. eax register with 16-bit and 8-bit name components. . . . . . 28 figure 8. integer data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. segment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10. segment usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11. floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. fpu status word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13. fpu control word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 14. fpu tag word register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15. packed decimal data register . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. precision real data registers . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17. mmx?/3dnow!? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18. mmx? technology data types . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19. 3dnow!? technology data types . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. eflags registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 21. control register 4 (cr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. control register 3 (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 23. control register 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 24. control register 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 25. control register 0 (cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 26. debug register dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 27. debug register dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 28. debug registers dr5 and dr4. . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 29. debug registers dr3, dr2, dr1, and dr0. . . . . . . . . . . . . . . . 43 figure 30. machine-check address register (mcar) . . . . . . . . . . . . . . . . 45 figure 31. machine-check type register (mctr) . . . . . . . . . . . . . . . . . . . 45 figure 32. test register 12 (tr12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 33. time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 34. extended feature enable register (efer) . . . . . . . . . . . . . . . 47 figure 35. syscall/sysret target address register (star) . . . . . . . 48 figure 36. write handling control register (whcr) . . . . . . . . . . . . . . . . 48
x list of figures amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 37. uc/wc cacheability control register (uwccr) . . . . . . . . . . 49 figure 38. processor state observability register (psor) . . . . . . . . . . . . 49 figure 39. page flush/invalidate register (pfir) . . . . . . . . . . . . . . . . . . . 50 figure 40. l2 tag or data location for amd-k6?-iiie+ processoredx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 41. l2 data eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 42. l2 tag information for amd-k6?-iiie+ processoreax . . . 52 figure 43. enhanced power management register (epmr) . . . . . . . . . . . 53 figure 44. memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 45. task state segment (tss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 46. 4-kbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 47. 4-mbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 48. page directory entry 4-kbyte page table (pde) . . . . . . . . . . . 58 figure 49. page directory entry 4-mbyte page table (pde) . . . . . . . . . . 58 figure 50. page table entry (pte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 51. application segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 52. system segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 53. gate descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 54. enhanced power management register (epmr) . . . . . . . . . . 144 figure 55. epm 16-byte i/o block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 56. bus divisor and voltage id control (bvc) field . . . . . . . . . . 147 figure 57. processor state observability register (psor)low- power versions of the processor . . . . . . . . . . . . . . . . . . . . . . . 148 figure 58. waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 59. bus state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 60. non-pipelined single-transfer memory read/write and write delayed by ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 61. misaligned single-transfer memory read and write . . . . . . 161 figure 62. burst reads and pipelined burst reads . . . . . . . . . . . . . . . . . 163 figure 63. burst writeback due to cache-line replacement . . . . . . . . . 165 figure 64. basic i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 65. misaligned i/o transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 66. basic hold/hlda operation . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 67. hold-initiated inquire hit to shared or exclusive line . . . 171 figure 68. hold-initiated inquire hit to modified line. . . . . . . . . . . . . 173 figure 69. ahold-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 70. ahold-initiated inquire hit to shared or exclusive line . . 177 figure 71. ahold-initiated inquire hit to modified line . . . . . . . . . . . 179 figure 72. ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
list of figures xi 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 73. boff# timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 74. basic locked operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 75. locked operation with boff# intervention. . . . . . . . . . . . . . 187 figure 76. interrupt acknowledge operation . . . . . . . . . . . . . . . . . . . . . . 189 figure 77. basic special bus cycle (halt cycle) . . . . . . . . . . . . . . . . . . . . 191 figure 78. shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 79. stop grant and stop clock modes, part 1 . . . . . . . . . . . . . . . . 194 figure 80. stop grant and stop clock modes, part 2 . . . . . . . . . . . . . . . . 195 figure 81. init-initiated transition from protected mode to real mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 82. l1 and l2 cache organization for the amd-k6?-iiie+ processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 83. l1 cache sector organization. . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 84. write handling control register (whcr) . . . . . . . . . . . . . . . 217 figure 85. write allocate logic mechanisms and conditions . . . . . . . . . 218 figure 86. page flush/invalidate register (pfir) . . . . . . . . . . . . . . . . . . 224 figure 87. uc/wc cacheability control register (uwccr) . . . . . . . . . 232 figure 88. external logic for supporting floating-point exceptions. . . 239 figure 89. smm memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 figure 90. tap state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 figure 91. l2 cache organization for amd-k6?-iiie+ processor . . . . . 265 figure 92. l2 cache sector and line organization . . . . . . . . . . . . . . . . . 265 figure 93. l2 tag or data location for the amd-k6?-iiie+ processoredx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 figure 94. l2 data - eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 figure 95. l2 tag information for the amd-k6?-iiie+ processoreax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 figure 96. lru byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 figure 97. debug register dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 figure 98. debug register dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 99. debug registers dr5 and dr4. . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 100. debug registers dr3, dr2, dr1, and dr0. . . . . . . . . . . . . . . 272 figure 101. clock control state transitions for standard-power versions of the amd-k6?-iiie+ processor . . . . . . . . . . . . . . . 278 figure 102. clock control state transitions for low-power versions of the amd-k6?-iiie+ processor . . . . . . . . . . . . . . . 279 figure 103. suggested component placement for cpga package . . . . . . 294 figure 104. clk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 105. key to timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
xii list of figures amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 106. output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 figure 107. maximum float delay timing . . . . . . . . . . . . . . . . . . . . . . . . . 312 figure 108. input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . 312 figure 109. reset and configuration timing . . . . . . . . . . . . . . . . . . . . . . . 313 figure 110. tck waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 figure 111. trst# timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 figure 112. test signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 figure 113. thermal model (cpga package) . . . . . . . . . . . . . . . . . . . . . . . 317 figure 114. power consumption and thermal resistance (cpga package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 figure 115. processor heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . 318 figure 116. measuring case temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 319 figure 117. voltage regulator placement . . . . . . . . . . . . . . . . . . . . . . . . . . 320 figure 118. airflow for a heatsink with fan . . . . . . . . . . . . . . . . . . . . . . . . 321 figure 119. airflow path in a dual-fan system . . . . . . . . . . . . . . . . . . . . . 321 figure 120. airflow path in an atx form-factor system . . . . . . . . . . . . . 322 figure 121. cpga connection diagram (top-side view) . . . . . . . . . . . . . 324 figure 122. cpga connection diagram (bottom-side view) . . . . . . . . . . 325 figure 123. obga connection diagram (top-side view) . . . . . . . . . . . . . 328 figure 124. obga connection diagram (bottom-side view) . . . . . . . . . . 329 figure 125. 321-pin staggered cpga package specification . . . . . . . . . . 333 figure 126. 349-ball obga package specification . . . . . . . . . . . . . . . . . . . 334
list of tables xiii 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information list of tables table 1. execution latency and throughput of execution units . . . . . 23 table 2. general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 3. general-purpose register doubleword, word, and byte names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 4. segment registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5. amd-k6?-iiie+ processor model-specific registers . . . . . . . 44 table 6. extended feature enable register (efer) definition . . . . . . 47 table 7. syscall/sysret target address register (star) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 8. memory management registers . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 9. application segment types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 10. system segment and gate types . . . . . . . . . . . . . . . . . . . . . . . . 61 table 11. summary of exceptions and interrupts . . . . . . . . . . . . . . . . . . . 62 table 12. integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 13. floating-point instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 14. mmx? instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 15. 3dnow!? instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 16. 3dnow!? technology dsp extensions . . . . . . . . . . . . . . . . . . . 90 table 17. processor-to-bus clock ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 18. output pin float conditions for vcc2 high/low. . . . . . . . . . 136 table 19. input pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 20. output pin float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 21. input/output pin float conditions. . . . . . . . . . . . . . . . . . . . . . 141 table 22. test pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 23. bus cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 24. special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 25. enhanced power management register (epmr) definition 145 table 26. epm 16-byte i/o block definition . . . . . . . . . . . . . . . . . . . . . . 146 table 27. bus divisor and voltage id control (bvc) definition . . . . . . 147 table 28. processor-to-bus clock ratios. . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 29. bus-cycle order during misaligned memory transfers . . . . 160 table 30. a[4:3] address-generation sequence during bursts . . . . . . . 162 table 31. bus-cycle order during misaligned i/o transfers . . . . . . . . . 167 table 32. interrupt acknowledge operation definition. . . . . . . . . . . . . 188 table 33. encodings for special bus cycles . . . . . . . . . . . . . . . . . . . . . . . 190 table 34. output signal state after reset . . . . . . . . . . . . . . . . . . . . . . 200 table 35. register state after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 36. pwt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 37. pcd signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 38. cache# signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 39. l1 and l2 cache states for read and write accesses . . . . . . 221
xiv list of tables amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 40. valid l1 and l2 cache states and effect of inquire cycles . 225 table 41. l1 and l2 cache states for snoops, flushes, and invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 42. ewbec settings and performance . . . . . . . . . . . . . . . . . . . . . 231 table 43. wc/uc memory type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 44. valid masks and range sizes for uwccr register . . . . . . . 234 table 45. initial state of registers in smm . . . . . . . . . . . . . . . . . . . . . . . 243 table 46. smm state-save area map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 47. smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 48. i/o trap doubleword configuration . . . . . . . . . . . . . . . . . . . . 248 table 49. i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 50. boundary scan bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . 257 table 51. device identification register . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 52. supported tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 53. tag versus data selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 54. dr7 len and rw definitions . . . . . . . . . . . . . . . . . . . . . . . . . 274 table 55. operating ranges for low-power amd-k6?-iiie+ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 56. operating ranges for standard-power amd-k6?-iiie+ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 57. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 table 58. dc characteristics for the amd-k6?-iiie+ processor . . . . . 289 table 59. power dissipation for low-power amd-k6?-iiie+ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 table 60. power dissipation for standard-power amd-k6?-iiie+ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 61. supported frequencies and voltages for low-power amd-k6?-iiie+ processors enabled with amd powernow!? technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 62. clk switching characteristics for 100-mhz bus operation . 298 table 63. clk switching characteristics for 66-mhz bus operation . . 299 table 64. output delay timings for 100-mhz bus operation . . . . . . . . 300 table 65. input setup and hold timings for 100-mhz bus operation . 302 table 66. output delay timings for 66-mhz bus operation . . . . . . . . . 304 table 67. input setup and hold timings for 66-mhz bus operation . . 306 table 68. reset and configuration signals for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 69. reset and configuration signals for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 70. tck waveform and trst# timing at 25 mhz . . . . . . . . . . . . 310 table 71. test signal timing at 25 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . 310 table 72. package thermal specification for low-power amd-k6?-iiie+ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
list of tables xv 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 73. package thermal specification for standard-power amd-k6?-iiie+ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 table 74. pin differences between the cpga and obga packages. . . 323 table 75. cpga pin designations by functional grouping . . . . . . . . . . 326 table 76. cpga pin designations for no connect, reserved, power, and ground pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 table 77. obga pin designations by functional grouping . . . . . . . . . . 330 table 78. obga pin designations for no connect, reserved, power, and ground pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 table 79. amd-k6?-iiie+ embedded processor valid ordering part number combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
xvi list of tables amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
revision history xvii 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information revision history date rev description september 2000 a initial published release september 2000 a second printing: revised trademarks. september 2000 a second printing: changed setting of nol2 bit on page 148. september 2000 a second printing: changed bus speed from 60 mhz to 66 mhz in note 4, table 58 on page 289. september 2000 a second printing: revised headings in table 59 on page 291, table 60 on page 292, and table 61 on page 292. changed note 2 in table 59 on page 291 and table 60 on page 292 to apply to 400-mhz parts only.
xviii revision history amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
about this data sheet xix 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information about this data sheet the amd-k6?-iii e+ embedded processor data sheet is the complete specification of the amd-k6?-iii e+ embedded processor. overview this data sheet is organized into the following sections: chapter 1, amd-k6?-iiie+ embedded processor on page 1, provides a list of the AMD-K6-IIIE+ processors distinguishing characteristics, a description of the key features, and a discussion about the super7? platform initiative. chapter 2, internal architecture on page 11, describes the functional elements of the advanced design techniques, known as the risc86 ? microarchitecture, implemented by the AMD-K6-IIIE+ processor. chapter 3, software environment on page 27, provides a general overview of the amd-k6-2e processors x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the AMD-K6-IIIE+ processors architecture and design implementation. chapter 4, logic symbol diagram on page 91, contains the AMD-K6-IIIE+ processor logic symbol diagram. chapter 5, signal descriptions on page 93, lists the signals and their descriptions alphabetically and by function. chapter 6, amd powernow!? technology on page 143, describes the enhanced power management features available on the low-power versions of the AMD-K6-IIIE+ processor. chapter 7, bus cycles on page 153, describes and illustrates the timing and relationship of bus signals during various types of bus cycles.
xx about this data sheet amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information chapter 8, power-on configuration and initialization on page 199, describes how the system logic resets the AMD-K6-IIIE+ processor using the reset signal. chapter 9, cache organization on page 205, describes the basic architecture and resources of the AMD-K6-IIIE+ processors internal caches. chapter 10, write merge buffer on page 229, describes the 8- byte write merge buffer and how merging multiple write cycles into a single write cycle ultimately increases overall system performance. chapter 11, floating-point and multimedia execution units on page 237, describes the AMD-K6-IIIE+ processors ieee 754- compatible and 854-compatible floating point execution unit, the multimedia and 3dnow!? technology execution units, and the floating-point and mmx?/3dnow! technology instruction compatibility. chapter 12, system management mode (smm) on page 241, describes smm, the state-save area, entry into and exit from smm, exceptions and interrupts in smm, memory allocation and addressing in smm, and the smi# and smiact# signals. chapter 13, test and debug on page 251, describes the various test and debug modes that enable the functional and manufacturing testing of systems and boards that use the AMD-K6-IIIE+ processor and that allow designers to debug the instruction execution of software components. chapter 14, clock control on page 277, describes the five modes of clock control supported by the AMD-K6-IIIE+ processor. chapter 15, electrical data on page 287, includes operating ranges, absolute ratings, dc characteristics, power dissipation data, power and grounding information, and decoupling recommendations. chapter 16, signal switching characteristics on page 297, provides tables listing valid delay, float, setup, and hold timing specifications for the AMD-K6-IIIE+ processor signals.
about this data sheet xxi 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information chapter 17, thermal design on page 315, lists the package thermal specifications, discusses how to measure case temperature, and provides layout and airflow considerations. chapter 18, pin designations on page 323, provides top- and bottom-view connection diagrams for each package type and lists the AMD-K6-IIIE+ processors pin designations by functional grouping. chapter 19, package specifications on page 333, provides diagrams showing the specifications for the 321-pin cpga package and the 349-ball obga package. chapter 20, ordering information on page 335, provides the ordering part number (opn) and valid opn combinations.
xxii about this data sheet amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 1 amd-k6?- iii e+ embedded processor 1 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 1 amd-k6?- iii e+ embedded processor the following are key features of the amd-k6?-iiie+ processor: n member of the amd-k6?e family of 32-bit embedded processors u brings the power, performance, and value of the amd-k6 family to the embedded market u enables improved time-to-market by leveraging existing hardware and software infrastructure and field-proven development tools u offers a wide software- and platform-compatible growth path with product longevity to help preserve development investments n functionally-compatible embedded version of the amd-k6-iii+ processor with internal 256-kbyte l2 cache u provides the highest super7? platform performance with reduced total system cost u microsoft ? windows ? compatible processor u x86 binary software compatible u supports real-time operating systems such as psos, qnx, rtxc, and vxworks n advanced 6-issue risc86 ? superscalar microarchitecture u ten parallel specialized execution units u multiple sophisticated x86-to-risc86 instruction decoders u advanced two-level branch prediction u speculative and out-of-order execution u register renaming and data forwarding u up to six risc86 instructions per clock n innovative u 320-kbyte total internal cache ? internal split, two-way set associative, 64-kbyte l1 cache - 32-kbyte instruction cache with additional 20-kbytes of predecode cache - 32-kbyte writeback dual-ported data cache - mesi protocol support ? internal full-speed, four-way set associative, 256-kbyte, l2 cache u multiport internal cache design enabling simultaneous 64-bit reads/writes of l1 and l2 caches n super7 platform is socket 7-compatible u leverages high-speed 100-mhz processor bus
2 amd-k6?- iii e+ embedded processor chapter 1 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information u 2x accelerated graphic port (agp) support u takes advantage of existing system support, logic integration, and designs for superior value u provides an easy upgrade path for embedded applications and a bridge to legacy applications n amd powernow!? technology dynamically manages power and performance u monitors application requirements for performance or power utilization u supports continuously varying operating frequency and voltage, delivering performance on demand while dissipating the lowest amount of power possible n 3dnow!? technology for better multimedia and audio performance u x86 instruction set extension accelerates 3d graphics and other single- precision floating-point compute-intensive operations u offers fast frame rates on high-resolution graphics applications, superior modeling of real-world environments and physics, life-like images and graphics, and big-screen sound and video u additional 3dnow! technology dsp instructions enhance communications applications u separate multiplier and alu for superscalar instruction execution n high-performance ieee 754-compatible and 854-compatible floating-point unit n high-performance industry-standard mmx? instructions u dual-integer alu for superscalar execution n industry-standard system management mode (smm) n ieee 1149.1 boundary scan n 321-pin ceramic pin grid array (cpga) or 349-ball organic ball grid array (obga) package n low-voltage 0.18-micron process technology u split-plane power with support for full 3.3 v i/o u lower core voltages enable low-power operation n operating frequencies u standard-power and standard-temperature devices: 400, 450, 500, and 550 mhz u low-power and extended-temperature devices: 400, 450, and 500 mhz
chapter 1 amd-k6?- iii e+ embedded processor 3 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 1.1 amd-k6?- iii e+ embedded processor features the innovative AMD-K6-IIIE+ processor brings industry-leading performance to embedded systems. its super7? platform-compatible, 321-pin ceramic pin grid array (cpga) or 349-ball organic ball grid array (obga) package enables embedded system designers to reduce time-to-market by leveraging todays cost-effective, industry-standard infrastructure. manufactured using amds 0.18 micron low-power process, the AMD-K6-IIIE+ processor incorporates the innovative and efficient risc86 ? microarchitecture, a 320-kbyte total internal cache, a fast 100 mhz frontside bus, and a powerful ieee 754-compatible and 854-compatible floating-point execution unit. the AMD-K6-IIIE+ processor also incorporates a superscalar mmx? unit and amds innovative 3dnow! technology for high-performance multimedia and 3d graphics operation. the AMD-K6-IIIE+ processor is a functionally compatible embedded version of the amd-k6-iii+ processor. the cache design provides a large 64-kbyte l1 cache and a 256-kbyte l2 cache operating at full processor speed on a backside bus. the size and speed of the cache memory subsystem gives the AMD-K6-IIIE+ processor a significant performance edge over competing socket 7 solutions. the low-power versions of the AMD-K6-IIIE+ processor also support amds enhanced power management features, called amd powernow! technology. the AMD-K6-IIIE+ processor is part of the amd-k6e family of embedded processors. within this family: n the amd-k6-2e processor provides the best value and performance for cost- sensitive embedded applications. n the amd-k6-2e+ with its 128-kbyte internal l2 cache offers higher performance balanced with cost. n the AMD-K6-IIIE+ with its 256-kbyte internal l2 cache offers the highest performance available for super7 and socket 7 platforms. all amd-k6e family processors in the cpga package share the same footprint and support the socket 7-compatible super7 platform. the amd-k6e family provides embedded designers with an assured growth plan and supply stability, along with product longevity. all amd-k6e family processors are x86-binary compatible, allowing preservation of the initial software investment. the AMD-K6-IIIE+ embedded processor is particularly well-suited for use in applications where high performance is required. it is designed to offer compelling, yet affordable, power and performance for high-end embedded applications, such as information appliances, set-top boxes, embedded pcs, point-of-sale terminals, public and private communications infrastructure, and industrial control.
4 amd-k6?- iii e+ embedded processor chapter 1 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the AMD-K6-IIIE+ embedded processor is available in two versions. n the low-power version operates at the lowest core voltage in order to offer the lowest available power and extended temperature ratings. enhanced power management features are provided via amd powernow! technology in the low- power versions of the processor. n the standard-power version has a 2.0-v core voltage and offers standard power and temperature specifications similar to desktop pc processors. innovative cache design for faster data access recognizing the benefits of a large and fast cache design in feeding performance- hungry applications, amd developed an innovative cache architecture that enhances the performance available for embedded applications based on the super7 platform. amds cache design innovations include: n an internal 256-kbyte l2 write-back cache operating at the full speed of the processor and complementing the 64-kbyte l1 cache, which is standard in all amd-k6 family processors. n a multiport internal cache design, enabling simultaneous 64-bit reads and writes to both the l1 cache and the l2 cache. n a 4-way set associative backside l2 cache design enabling optimal data management and external frontside data bus bandwidth efficiency. the processor's multiport internal cache design enables both the 64-kbyte l1 cache and the 256-kbyte l2 cache to perform simultaneous 64-bit read and write operations in a clock cycle. this multiport capability allows data to be processed faster and more efficiently than non-multiported designs. in addition, the processor core can access both l1 and l2 caches simultaneously, which further enhances overall cpu throughput. the cache design is exceptionally fast, with the backside 256-kbyte l2 cache operating at full processor speed. for example, the internal l2 cache of an AMD-K6-IIIE+/450 processor operates at 450 mhz and provides nine times the peak bandwidth of an external l2 cache operating at 100 mhz. the maximum peak bandwidth of an external l2 cache operating at 100 mhz is 800 mbytes/s, while an internal l2 cache operating at 450 mhz delivers a maximum peak bandwidth of 3,600 mbytes/s per port. because the internal l2 cache of the AMD-K6-IIIE+ processor is dual-ported for simultaneous reads and writes, the total peak bandwidth is doubled to 7,200 mbytes/s, resulting in a maximum peak bandwidth nine times as large as a 100-mhz cache implementation.
chapter 1 amd-k6?- iii e+ embedded processor 5 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 3dnow!? technology the AMD-K6-IIIE+ processor supports amds 3dnow! technology, an extension to the x86 instruction set that includes 21 new instructions to accelerate 3d graphics and other single-precision floating-point compute intensive operations. 3dnow! technology was defined and implemented in collaboration with microsoft, application developers, and graphics vendors, and has received an enthusiastic reception. it is compatible with todays existing x86 software and requires no operating system support, thereby enabling a broad class of applications to benefit from 3dnow! technology. the worldwide installed base of 3dnow! technology-enhanced pcs has grown to more than 25 million desktop and notebook systems, revolutionizing the 3d experience with up to four times the peak floating-point performance of previous sixth generation solutions. support for 3dnow! technology exists today in leading industry- standard apis, including microsoft ? directx and sgis opengl apis. additionally, numerous hardware and software products have been optimized for 3dnow! technology. amd is now bringing this advanced capability to embedded systems. 3dnow! technology enables fast frame rates on high-resolution 3d-rendered scenes, realistic physical modeling of real-world environments, sharp and detailed 3d imaging, smooth video playback, and theater-quality audio. in addition, the AMD-K6-IIIE+ processor adds support for five new digital signal processing (dsp) instructions, developed to enhance the performance of communications applications, including soft xdsl modems, mp3 recording, and dolby digital and surround sound processing.
6 amd-k6?- iii e+ embedded processor chapter 1 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information amd powernow!? technology for enhanced power management amd has added a number of new power management features to the low-power versions of the AMD-K6-IIIE+ processor. collectively, these hardware and software features are called amd powernow!? technology. amd powernow! technology allows the AMD-K6-IIIE+ processor to run at different frequencies and voltages, depending on the applications need for maximum performance or the most efficient power utilization. amd powernow! technology includes amds unique automatic mode feature, which allows the system to monitor application usage and to continuously vary the operating frequency and voltage, delivering performance on demand while dissipating the lowest amount of power possible. n when application demands require the processor to run at maximum performance, the amd powernow! technology steps up the performance to meet the demand. n as platform demand for performance subsides, amd powernow! technology can dynamically drop into a lower power state. amd powernow! technology enables embedded products to dynamically manage power and performance. system management mode and other power management features the AMD-K6-IIIE+ processor includes the complete industry-standard system management mode (smm), which is critical to system resource and power management. the AMD-K6-IIIE+ processor also features the industry-standard stop-clock (stpclk#) control circuitry and the halt instruction, both required for implementing the acpi power management specification. microarchitecture the AMD-K6-IIIE+ processors 6-issue risc86 microarchitecture is a decoupled decode/execution superscalar design that implements state-of-the-art design techniques to achieve leading-edge performance. advanced design techniques implemented in the AMD-K6-IIIE+ processor include multiple x86 instruction decode, single-clock internal risc operations, ten execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming.
chapter 1 amd-k6?- iii e+ embedded processor 7 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information in addition, the processor supports advanced branch prediction logic by implementing an 8192-entry branch history table, a branch target cache, and a return address stack, which combine to deliver better than a 95% prediction rate. these design techniques enable the AMD-K6-IIIE+ processor to issue, execute, and retire multiple x86 instructions per clock, resulting in excellent scaleable performance. industry-standard x86 architecture the AMD-K6-IIIE+ processor is x86 binary code compatible. amds extensive experience through six generations of x86 processors has been carefully integrated into the processor to enable compatibility with windows ? 98, windows 95, windows 3.x, windows nt, dos, linux, os/2, unix, solaris, netware ? , and other leading x86 operating systems and applications. the AMD-K6-IIIE+ processor is also compatible with leading real-time operating systems (rtos) commonly used in embedded applications, such as psos, qnx, rtxc, and vxworks. additionally, the amd fusione86 sm third-party tool support program offers extensive development support for AMD-K6-IIIE+ processor designs. the AMD-K6-IIIE+ processor is super7 and socket 7-compatible. the super7 platform is an extension to the popular and robust socket 7 platform. see super7? platform on page 8 for more information. amd is the worlds second-leading supplier of pc processors compatible with the windows operating system, having shipped more than 120 million x86 microprocessors, including more than 60 million windows-compatible processors. the AMD-K6-IIIE+ processor for embedded applications is the latest member in this long line of processors. with its combination of state-of-the-art features, industry-leading performance, high-performance 3dnow! technology and multimedia engines, x86 compatibility, and low-cost infrastructure, the AMD-K6-IIIE+ processor is the superior choice for high-performance embedded systems. 1.2 process technology the AMD-K6-IIIE+ processor is implemented using an amd-developed, state-of-the- art low power 0.18-micron process technology. this process technology features a split-plane design that enables the AMD-K6-IIIE+ processor to deliver excellent performance solutions while utilizing a lower processor core voltage, which results in lower power consumption, while the i/o portion operates at the industry-standard 3.3-v level.
8 amd-k6?- iii e+ embedded processor chapter 1 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 1.3 super7? platform the super7 platform is an extension to the popular socket 7 platform. amd and its industry partners have invested in the future of socket 7 with the super7 platform initiative. the goal of the initiative is to maintain the competitive vitality of the socket 7 infrastructure through a series of enhancements, including the development of an industry-standard 100-mhz processor bus protocol. in addition to the 100-mhz processor bus protocol, the super7 initiative includes the introduction of chipsets that support the agp specification, and support for a backside l2 cache. currently, over 40 motherboard vendors and all major bios and chipset vendors offer super7-based products. all amd-k6 embedded processors in cpga packages remain pin compatible with existing socket 7 solutions; however, for maximum system performance, the AMD-K6-IIIE+ processor works optimally in super7 designs that incorporate advanced features such as support for the 100-mhz frontside bus and agp graphics. 100-mhz processor bus the AMD-K6-IIIE+ processor supports a 100-mhz, 800 mbyte/second frontside bus to provide a high-speed interface to super7 platform-based chipsets. the 100-mhz interface speeds up access to main memory by 50 percent over the 66-mhz socket 7 interfaceresulting in a significant 10 percent increase in overall system performance. accelerated graphics port support accelerated graphics port (agp) support improves the performance of video graphics systems that have small amounts of video memory on the graphics card. the industry-standard agp specification enables a 133-mhz graphics interface and will scale to even higher levels of performance. support for backside l2 cache the super7 platform has the headroom to support higher-performance amd-k6 processors like the AMD-K6-IIIE+ processor, which features a full-speed, internal backside 256-kbyte l2 cache designed to enable new levels of performance to leading-edge embedded systems.
chapter 1 amd-k6?- iii e+ embedded processor 9 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information super7? platform advantages the super7 platform: n delivers performance and features competitive with alternate platforms at the same clock speed, and at a significantly lower cost n takes advantage of existing system designs for superior value n enables oems and resellers to take advantage of mature, high-volume infrastructure supported by multiple bios, chipset, graphics, and motherboard suppliers n reduces inventory and design costs with one motherboard for a wide range of products n builds on a huge installed base of more than 100 million motherboards n provides an easy upgrade path for embedded applications, as well as a bridge to legacy applications by taking advantage of the low-cost, mature socket 7 infrastructure, the super7 platform will continue to provide superior value and leading-edge performance for embedded systems.
10 amd-k6?- iii e+ embedded processor chapter 1 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 2 internal architecture 11 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 2 internal architecture the AMD-K6-IIIE+ processor implements advanced design techniques known as the risc86 microarchitecture. the risc86 microarchitecture is a decoupled decode/execution design approach that yields superior sixth-generation performance for x86-based software. this chapter describes the techniques used and the functional elements of the risc86 microarchitecture. 2.1 microarchitecture overview when discussing processor design, it is important to understand the terms architecture , microarchitecture , and design implementation . n a rchitecture refers to the instruction set and features of a processor that are visible to software programs running on the processor. the architecture determines what software the processor can run. the architecture of the AMD-K6-IIIE+ processor is the industry-standard x86 instruction set. n m icroarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals. the amd-k6 family of processors are based on a sophisticated risc core known as the enhanced risc86 microarchitecture. the enhanced risc86 microarchitecture is an advanced, second-order decoupled decode/execution design approach that enables industry-leading performance for x86-based software. n d esign implementation refers to the actual logic and circuit designs from which the processor is created according to the microarchitecture specifications.
12 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information enhanced risc86 ? microarchitecture the enhanced risc86 microarchitecture defines the characteristics of the amd-k6 family of processors. the innovative risc86 microarchitecture approach implements the x86 instruction set by internally translating x86 instructions into risc86 operations. these risc86 operations were specially designed to include direct support for the x86 instruction set while observing the risc performance principles of fixed length encoding, regularized instruction fields, and a large register set. the enhanced risc86 microarchitecture used in the AMD-K6-IIIE+ processor enables higher processor core performance and promotes straightforward extensions, such as those added in the current AMD-K6-IIIE+ processor and those planned for the future. instead of directly executing complex x86 instructions, which have lengths of 1 to 15 bytes, the AMD-K6-IIIE+ processor executes the simpler and easier fixed-length risc86 operations, while maintaining the instruction coding efficiencies found in x86 programs. the AMD-K6-IIIE+ processor contains parallel decoders, a centralized risc86 operation scheduler, and ten execution units that support su perscalar operationmultiple decode, execution, and retirementof x86 instructions. these elements are packed into an aggressive and highly efficient six-stage pipeline. amd-k6?- iii e+ processor block diagram as shown in figure 1 on page 13, the high-performance, out-of-order execution engine of the AMD-K6-IIIE+ processor is mated to a split, level-one, 64-kbyte, writeback cache with 32 kbytes of instruction cache and 32 kbytes of data cache. backing up the level-one (l1) cache is a large, unified, level-two (l2), 256-kbyte, writeback cache. the l1 instruction cache feeds the decoders and, in turn, the decoders feed the scheduler. the icu issues and retires risc86 operations contained in the scheduler. the system bus interface is an industry-standard 64-bit super7 and socket 7 demultiplexed bus. the AMD-K6-IIIE+ processor combines the latest in processor microarchitecture to provide the highest x86 performance for todays computational systems. the AMD-K6-IIIE+ processor offers true sixth-generation performance and x86 binary software compatibility.
chapter 2 internal architecture 13 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 1. amd-k6?- iii e+ processor block diagram decoders decoding of the x86 instructions begins when the on-chip l1 instruction cache is filled. predecode logic determines the length of an x86 instruction on a byte-by-byte basis. this predecode information is stored, along with the x86 instructions, in the l1 instruction cache, to be used later by the decoders. the decoders translate on-the-fly, with no additional latency, up to two x86 instructions per clock into risc86 operations. note: in this chapter, clock refers to a processor clock. the AMD-K6-IIIE+ processor categorizes x86 instructions into three types of decodesshort, long, and vector. the decoders process either two short, one long, or one vector decode at a time. the three types of decodes have the following characteristics: n short decodesx86 instructions less than or equal to seven bytes in length 6wruh 8qlw 6wruh 4xhxh ,qvwuxfwlrq &rqwuro8qlw 6fkhgxohu %xiihu 5,6& 6l[5,6& 6l[5,6& ? ? 2shudwlrq,vvxh 2shudwlrq,vvxh )rxu 5,6& 'hfrgh 2xwri2ughu 2xwri2ughu ([hfxwlrq(qjlqh ([hfxwlrq(qjlqh /hyho2qh'xdo3ruw'dwd&dfkh .%\wh (qwu\'7/% .%\wh/hyho2qh,qvwuxfwlrq&dfkh .%\wh3uhghfrgh&dfkh 'xdo,qvwuxfwlrq'hfrghuv [wr5,6& %\wh)hwfk /rdg 8qlw )ordwlqj3rlqw 8qlw %udqfk 5hvroxwlrq8qlw 3uhghfrgh /rjlf /hyho2qh&dfkh &rqwuroohu 0+] 6xshu? %xv ,qwhuidfh /hyho7zr &dfkh .%\wh 5hjlvwhu8qlw; ,qwhjhu 0xowlphgld'1rz 70 5hjlvwhu8qlw< ,qwhjhu 0xowlphgld'1rz %udqfk/rjlf (qwu\%+7 (qwu\%7& (qwu\5$6 (qwu\,7/%
14 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information n long decodesx86 instructions less than or equal to 11 bytes in length n vector decodescomplex x86 instructions short and long decodes are processed completely within the decoders. vector decodes are started by the decoders and then completed by fetched sequences from an on-chip rom. after decoding, the risc86 operations are delivered to the scheduler for dispatching to the executions units. scheduler/instruction control unit the centralized scheduler or buffer is managed by the instruction control unit (icu). the icu buffers and manages up to 24 risc86 operations at a time. this equals from 6 to 12 x86 instructions. this buffer size (24) is perfectly matched to the processors six-stage risc86 pipeline and four risc86-operations decode rate. the scheduler accepts as many as four risc86 operations at a time from the decoders and retires up to four risc86 operations per clock cycle. the icu is capable of simultaneously issuing up to six risc86 operations at a time to the execution units. this consists of the following types of operations: n memory load operation n memory store operation n complex integer, mmx or 3dnow! register operation n simple integer, mmx or 3dnow! register operation n floating-point register operation n branch condition evaluation registers when managing the risc86 operations, the icu uses 69 physical registers contained within the risc86 microarchitecture. n forty-eight of the physical registers are located in a general register file. ? twenty-four of these are rename registers. ? the other twenty-four are committed or architectural registers, consisting of 16 scratch registers and 8 registers that correspond to the x86 general-purpose registers eax, ebx, ecx, edx, ebp, esp, esi, and edi.
chapter 2 internal architecture 15 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information n an analogous set of 21 registers is available specifically for mmx and 3dnow! operations. ? twelve of these are mmx/3dnow! rename registers. n nine are mmx/3dnow! committed or architectural registers, consisting of one scratch register and eight registers that correspond to the mmx registers (mm0Cmm7, as shown in figure 17 on page 35. branch logic the AMD-K6-IIIE+ processor is designed with highly sophisticated dynamic branch logic consisting of the following: n branch history/prediction table n branch target cache n return address stack the AMD-K6-IIIE+ processor implements a two-level branch prediction scheme based on an 8192-entry branch history table. the branch history table stores prediction information that is used for predicting conditional branches. because the branch history table does not store predicted target addresses, special address alus calculate target addresses on the fly during instruction decode. the branch target cache augments predicted branch performance by avoiding a one clock cache-fetch penalty. this specialized target cache does this by supplying the first 16 bytes of target instructions to the decoders when branches are predicted. the return address stack is a unique device specifically designed for optimizing call and return pairs. in summary, the AMD-K6-IIIE+ processor uses dynamic branch logic to minimize delays due to the branch instructions that are common in x86 software. 3dnow!? technology amd has taken a lead role in improving the multimedia and 3d capabilities of the x86 processor family with the introduction of 3dnow! technology, which uses a packed, single-precision, floating-point data format and single instruction multiple data (simd) operations based on the mmx technology model.
16 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 2.2 cache, instruction prefetch, and predecode bits the writeback level-one (l1) cache on the AMD-K6-IIIE+ processor is organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the level-two (l2) cache is 256 kbytes, and is organized as a unified, four-way set-associative cache. the cache line size is 32 bytes, and lines are fetched from external memory using an efficient pipelined burst transaction. as the l1 instruction cache is filled from the l2 cache or from external memory, each instruction byte is analyzed for instruction boundaries using predecoding logic. predecoding annotates information (5 bits per byte) to each instruction byte that later enables the decoders to efficiently decode multiple instructions simultaneously. cache the processor cache design takes advantage of a sectored organization (see figure 2). each sector consists of 64 bytes configured as two 32-byte cache lines. the two cache lines of a sector share a common tag but have separate pairs of mesi (modified, exclusive, shared, invalid) bits that track the state of each cache line. figure 2. cache sector organization two forms of cache misses and associated cache fills can take placea tag-miss cache fill and a tag-hit cache fill. n tag-miss cache fill the l1 cache miss is due to a tag mismatch, in which case the required cache line is filled either from the l2 cache or from external memory, and the l1 cache line within the sector that was not required is marked as invalid. n tag-hit cache fill the address matches the tag, but the requested cache line is marked as invalid. the required l1 cache line is filled from the l2 cache or from external memory, and the l1 cache line within the sector that is not required remains in the same cache state. tag address cache line 0 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits mesi bits cache line 1 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits mesi bits
chapter 2 internal architecture 17 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information prefetching the AMD-K6-IIIE+ processor conditionally performs cache prefetching, which results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. from the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. the 3dnow! technology includes an instruction called prefetch that allows a cache line to be prefetched into the l1 data cache and the l2 cache. the prefetch instruction format is defined in table 15, 3dnow!? instructions, on page 89. for more detailed information, see the 3dnow!? technology manual , order# 21928. predecode bits decoding x86 instructions is particularly difficult because the instructions are variable-length and can be from 1 to 15 bytes long. predecode logic supplies the five predecode bits that are associated with each instruction byte. the predecode bits indicate the number of bytes to the start of the next x86 instruction. the predecode bits are stored in an extended instruction cache alongside each x86 instruction byte as shown in figure 2 on page 16. the predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. 2.3 instruction fetch and decode instruction fetch the processor can fetch up to 16 bytes per clock out of the l1 instruction cache or branch target cache. the fetched information is placed into a 16-byte instruction buffer that feeds directly into the decoders (see figure 3 on page 18). fetching can occur along a single execution stream with up to seven outstanding branches taken. the instruction fetch logic is capable of retrieving any 16 contiguous bytes of information within a 32-byte boundary. there is no additional penalty when the 16 bytes of instructions lie across a cache line boundary. the instruction bytes are loaded into the instruction buffer as they are consumed by the decoders. although instructions can be consumed with byte granularity, the instruction buffer is managed on a memory-aligned word
18 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information (two bytes) organization. therefore, instructions are loaded and replaced with word granularity. when a control transfer occurssuch as a jmp instructionthe entire instruction buffer is flushed and reloaded with a new set of 16 instruction bytes. figure 3. the instruction buffer instruction decode the AMD-K6-IIIE+ processor decode logic is designed to decode multiple x86 instructions per clock (see figure 4 on page 19). the decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual instruction boundaries, and generates risc86 operations from these x86 instructions. risc86 operations are fixed-length internal instructions. most risc86 operations execute in a single clock. risc86 operations are combined to perform every function of the x86 instruction set. some x86 instructions are decoded into as few as zero risc86 operationsfor instance a nopor one risc86 16 instruction bytes plus 16 sets of predecode bits branch-target cache 16 x 16 by tes 2:1 instruction buffer 16 bytes 16 bytes branch target address adders return address stack 16 x 16 bytes 32-kbyte level-one instruction cache fetch unit
chapter 2 internal architecture 19 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information operationa register-to-register add. more complex x86 instructions are decoded into several risc86 operations. figure 4. amd-k6?- iii e+ processor decode logic the AMD-K6-IIIE+ processor uses a combination of decoders to convert x86 instructions into risc86 operations. the hardware consists of three sets of decoderstwo parallel short decoders, one long decoder, and one vector decoder. parallel short decoders. the two parallel short decoders translate the most commonly-used x86 instructions (moves, shifts, branches, alu, fpu) and the extensions to the x86 instruction set (including mmx and 3dnow! instructions) into zero, one, or two risc86 operations each. the short decoders only operate on x86 instructions that are up to seven bytes long. in addition, instruction buffer 4 risc86 operations long decoder short decoder #1 short decoder #2 vector address vector decoder risc86 ? sequencer on-chip rom
20 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information they are designed to decode up to two x86 instructions per clock. long decoder. the commonly-used x86 instructions that are greater than seven bytes but not more than 11 bytes long and less-commonly-used x86 instructions that are up to seven bytes long are handled by the long decoder. the long decoder only performs one decode per clock and generates up to four risc86 operations. vector decoder. all other translations (complex instructions, serializing conditions, interrupts and exceptions, etc.) are handled by a combination of the vector decoder and risc86 operation sequences fetched from an on-chip rom. for complex operations, the vector decoder logic provides the first set of risc86 operations and a vector (initial rom address) to a sequence of further risc86 operations. the same types of risc86 operations are fetched from the rom as those that are generated by the hardware decoders. note: although all three sets of decoders are simultaneously fed a copy of the instruction buffer contents, only one of the three types of decoders is used during any one decode clock. grouped operations. the decoders or the on-chip risc86 rom always generate a group of four risc86 operations. for decodes that cannot fill the entire group with four risc86 operations, risc86 nop operations are placed in the empty locations of the grouping. for example, a long-decoded x86 instruction that converts to only three risc86 operations is padded with a single risc86 nop operation and then passed to the scheduler. up to six groups or 24 risc86 operations can be placed in the scheduler at a time. floating point instructions. all of the common, and a few of the uncommon, floating-point instructions (also known as esc instructions) are hardware decoded as short decodes. this decode generates a risc86 floating-point operation and, optionally, an associated floating-point load or store operation. floating-point or esc instruction decode is only allowed in the first short decoder, but non-esc instructions can be decoded simultaneously by the second short decoder along with an esc instruction decode in the first short decoder.
chapter 2 internal architecture 21 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information mmx? and 3dnow!? instructions. all of the mmx and 3dnow! instructions, with the exception of the emms, femms, and prefetch instructions, are hardware decoded as short decodes. the mmx instruction decode generates a risc86 mmx operation and, optionally, an associated mmx load or store operation. a 3dnow! instruction decode generates a risc86 3dnow! operation and, optionally, an associated load or store operation. mmx and 3dnow! instructions can be decoded in either or both of the short decoders. 2.4 centralized scheduler the scheduler is the heart of the AMD-K6-IIIE+ processor (see figure 5 on page 22). it contains the logic necessary to manage out-of-order execution, data forwarding, register renaming, simultaneous issue and retirement of multiple risc86 operations, and speculative execution. the schedulers buffer can hold up to 24 risc86 operations. this equates to a maximum of 12 x86 instructions. the scheduler can issue risc86 operations from any of the 24 locations in the buffer. when possible, the scheduler can simultaneously issue a risc86 operation to any available execution unit (store, load, branch, register x integer/multimedia, register y integer/multimedia, or floating-point). in total, the scheduler can issue up to six and retire up to four risc86 operations per clock. the main advantage of the scheduler and its operation buffer is the ability to examine an x86 instruction window equal to 12 x86 instructions at one time. this advantage is due to the fact that the scheduler operates on the risc86 operations in parallel and allows the AMD-K6-IIIE+ processor to perform dynamic on-the-fly instruction code scheduling for optimized execution. although the scheduler can issue risc86 operations for out-of-order execution, it always retires x86 instructions in order.
22 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 5. amd-k6?- iii e+ processor scheduler 2.5 execution units the AMD-K6-IIIE+ processor contains ten parallel execution unitsstore, load, integer x alu, integer y alu, mmx alu (x), mmx alu (y), mmx/3dnow! multiplier, 3dnow! alu, floating-point, and branch condition. each unit is independent and capable of handling the risc86 operations issued to it. table 1 on page 23 details the execution units, functions performed within these units, operation latency, and operation throughput. note that the integer, mmx, and 3dnow! execution units share the register x and y issue pipelines. see register x and y pipelines on page 24. the store and load execution units are two-stage pipelined designs. n the store unit performs data writes and register calculation for lea/push instructions. data memory and register risc86 operation buffer risc86 issue buses risc86 #0 risc86 #1 risc86 #2 risc86 #3 centralized risc86 ? operation scheduler from decode logic
chapter 2 internal architecture 23 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information writes from stores are available after one clock. store operations are held in a store queue prior to execution. from there, they execute in order. n the load unit performs data memory reads. data is available from the load unit after two clocks. the integer x execution unit can operate on all alu operations, multiplies, divides (signed and unsigned), shifts, and rotates. the integer y execution unit can operate on the basic word and doubleword alu operationsadd, and, cmp, or, sub, xor, zero-extend and sign-extend operands. the branch condition unit is separate from the branch prediction logic (see branch-prediction logic on page 25) in that it resolves conditional branches such as jcc and loop after the branch condition has been evaluated. table 1. execution latency and throughput of execution units functional unit function latency throughput store lea/push, address (pipelined) 1 1 memory store (pipelined) 1 1 load memory loads (pipelined) 2 1 integer x integer alu 1 1 integer multiply 2C3 2C3 integer shift 1 1 multimedia (processes mmx instructions) mmx alu 1 1 mmx shifts, packs, unpack 1 1 mmx multiply 2 1 integer y basic alu (16-bit and 32-bit operands) 1 1 branch resolves branch conditions 1 1 fpu fadd, fsub, fmul 2 2 3dnow! 3dnow! alu 2 1 3dnow! multiply 2 1 3dnow! convert 2 1
24 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information register x and y pipelines the functional units that execute mmx and 3dnow! instructions share pipeline control with the integer x and integer y units. the register x and y functional units are attached to the issue bus for the register x execution pipeline or the issue bus for the register y execution pipeline or both. each register pipeline has dedicated resources that consist of an integer execution unit and an mmx alu execution unit, therefore allowing superscalar operation on integer and mmx instructions. in addition, both the x and y issue buses are connected to the 3dnow! alu, the mmx/3dnow! multiplier and mmx shifter, which allows the appropriate risc86 operation to be issued through either bus. figure 6 shows the details of the x and y register pipelines. figure 6. register x and y pipeline functional units mmx/ 3dnow! multiplier integer x alu mmx alu mmx shifter 3dnow! alu mmx alu integer y alu scheduler buffer (24 risc86 ? operations) issue bus for the register x execution pipeline issue bus for the register y execution pipeline
chapter 2 internal architecture 25 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 2.6 branch-prediction logic sophisticated branch logic that can minimize or hide the impact of changes in program flow is designed into the AMD-K6-IIIE+ processor. branches in x86 code fit into two categories: n unconditional branches always change program flow (that is, the branches are always taken) n c onditional branches may or may not divert program flow (that is, the branches are taken or not-taken). when a conditional branch is not taken, the processor simply continues decoding and executing the next instructions in memory. typical applications have up to 10% of unconditional branches and another 10% to 20% conditional branches. the AMD-K6-IIIE+ processor branch logic has been designed to handle this type of program behavior and to minimize its negative effects on instruction execution, such as stalls due to delayed instruction fetching and the draining of the processor pipeline. the branch logic contains an 8192-entry branch history table, a 16-entry by 16-byte branch target cache, a 16-entry return address stack, and a branch execution unit. branch history table the AMD-K6-IIIE+ processor handles unconditional branches without any penalty by redirecting instruction fetching to the target address of the unconditional branch. however, conditional branches require the use of the dynamic branch-prediction mechanism built into the AMD-K6-IIIE+ processor. a two-level adaptive history algorithm is implemented in an 8192-entry branch history table. this table stores executed branch information, predicts individual branches, and predicts the behavior of groups of branches. to accommodate the large branch history table, the AMD-K6-IIIE+ processor does not store predicted target addresses. instead, the branch target addresses are calculated on-the-fly using alus during the decode stage. the adders calculate all possible target addresses before the instructions are fully decoded and the processor chooses which addresses are valid.
26 internal architecture chapter 2 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information branch target cache to avoid a one clock cache-fetch penalty when a branch is predicted taken, a built-in branch target cache supplies the first 16 bytes of instructions directly to the instruction buffer (assuming the target address hits this cache). (see figure 3 on page 18.) the branch target cache is organized as 16 entries of 16 bytes. in total, the branch prediction logic achieves branch prediction rates greater than 95%. return address stack the return address stack is a special device designed to optimize call and ret pairs. software is typically compiled with subroutines that are frequently called from various places in a program. this is usually done to save space. entry into the subroutine occurs with the execution of a call instruction. at that time, the processor pushes the address of the next instruction in memory following the call instruction onto the stack (allocated space in memory). when the processor encounters a ret instruction (within or at the end of the subroutine), the branch logic pops the address from the stack and begins fetching from that location. to avoid the latency of main memory accesses during call and ret operations, the return address stack caches the pushed addresses. branch execution unit the branch execution unit enables efficient speculative execution. this unit gives the processor the ability to execute instructions beyond conditional branches before knowing whether the branch prediction was correct. the AMD-K6-IIIE+ processor does not permanently update the x86 registers or memory locations until all speculatively executed conditional branch instructions are resolved. when a prediction is incorrect, the processor backs out to the point of the mispredicted branch instruction and restores all registers. the AMD-K6-IIIE+ processor can support up to seven outstanding branches.
chapter 3 software environment 27 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 3 software environment this chapter provides a general overview of the AMD-K6-IIIE+ processors x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the AMD-K6-IIIE+ processor architecture and design implementation. the AMD-K6-IIIE+ processor implements the same ten model- specific registers (msrs) as the amd-k6-2 and amd-k6-2e processors model 8/[f:8], and the bits and fields within these ten msrs are defined identically. the AMD-K6-IIIE+ processor supports an additional msr for cache control. the low-power versions of the AMD-K6-IIIE+ processor support a twelfth msr to control the amd powernow! technology functions. see model-specific registers (msr) on page 44 for the msr definitions. the model number for the AMD-K6-IIIE+ processor is model d/[3:0], where the actual stepping can be any value in the range [3:0]. 3.1 registers the AMD-K6-IIIE+ processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, mmx/3dnow!, eflags, control, task, debug, test, and descriptor/memory-management registers. in addition, this chapter provides information on the AMD-K6-IIIE+ processor msrs. note: areas of the register designated as reserved should not be modified by software.
28 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information general-purpose registers the eight 32-bit x86 general-purpose registers are used to hold integer data or memory pointers used by instructions. table 2 contains a list of the general-purpose registers and the functions for which they are used. in order to support byte and word operations, eax, ebx, ecx, and edx can also be used as 8-bit and 16-bit registers. the shorter registers are overlaid on the longer ones. for example, the name of the 16-bit version of eax is ax (low 16 bits of eax) and the 8-bit names for ax are ah (high order bits) and al (low order bits). the same naming convention applies to ebx, ecx, and edx. edi, esi, esp, and ebp can be used as smaller 16-bit registers called di, si, sp, and bp respectively, but these registers do not have 8-bit versions. figure 7 shows the eax register with its name components, and table 3 on page 29 lists the doubleword (32-bit) general-purpose registers and their corresponding word (16-bit) and byte (8-bit) versions. figure 7. eax register with 16-bit and 8-bit name components table 2. general-purpose registers register function eax commonly used as an accumulator ebx commonly used as a pointer ecx commonly used for counting in loop operations edx commonly used to hold i/o information and to pass parameters edi commonly used as a destination pointer by the es segment esi commonly used as a source pointer by the ds segment esp used to point to the stack segment ebp used to point to data within the stack segment 87 0 15 16 31 eax ax ah al
chapter 3 software environment 29 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information integer data types four types of data are used in general-purpose registersbyte, word, doubleword, and quadword integers. figure 8 shows the format of the integer data registers. figure 8. integer data registers table 3. general-purpose register doubleword, word, and byte names 32-bit name (doubleword) 16-bit name (word) 8-bit name (high-order bits) 8-bit name (low-order bits) eax ax ah al ebx bx bh bl ecx cx ch cl edx dx dh dl edi di CC esi si C C esp sp C C ebp bp C C 15 0 31 0 precision 32 bits precision 16 bits word integer doubleword integer 70 precision 8 bits byte integer 63 0 precision 64 bits quadword integer
30 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information segment registers the six 16-bit segment registers are used as pointers to areas (segments) of memory. table 4 lists the segment registers and their functions. figure 9 shows the format for all six segment registers. figure 9. segment register segment usage the operating system determines the type of memory model that is implemented. the segment register usage is determined by the operating systems memory model. in a real mode memory model, the segment register points to the base address in memory. in a protected mode memory model the segment register is called a selector and it selects a segment descriptor in a descriptor table. this descriptor contains a pointer to the base of the segment, the limit of the segment, and various protection attributes. for more information on descriptor formats, see descriptors and gates on page 59. figure 10 on page 31 shows segment usage for real mode and protected mode memory models. table 4. segment registers segment register segment register function cs code segment, where instructions are located ds data segment, where data is located es data segment, where data is located fs data segment, where data is located gs data segment, where data is located ss stack segment 0 15
chapter 3 software environment 31 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 10. segment usage instruction pointer the instruction pointer (eip or ip) is used in conjunction with the code segment register (cs). the instruction pointer is either a 32-bit register (eip) or a 16-bit register (ip) that keeps track of where the next instruction resides within memory. this register cannot be directly manipulated, but can be altered by modifying return pointers when a jmp or call instruction is used. floating-point registers the floating-point execution unit in the AMD-K6-IIIE+ processor is designed to perform mathematical operations on non-integer numbers. this floating-point unit conforms to the ieee 754 and 854 standards and uses several registers to meet these standardseight numeric floating-point registers, a status word register, a control word register, and a tag word register. segment register real mode memory model segment selector physical memory protected mode memory model base descriptor table physical memory segment base base limit base limit segment base
32 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the eight floating-point registers are physically 80 bits wide and labeled fpr0Cfpr7. figure 11 shows the format of the floating-point registers. see floating-point register data types on page 34 for information on allowable floating-point data types. figure 11. floating-point register the 16-bit fpu status word register contains information about the state of the floating-point unit. figure 12 shows the format of the fpu status word register. figure 12. fpu status word register 64 63 0 78 79 sign exponent significand 9876543210 10 11 12 13 14 15 p e o e e s c 0 c 1 i e z e u e s f tosp c 3 b c 2 d e symbol description bits b fpu busy 15 c3 condition code 14 tosp top of stack pointer 13C11 c2 condition code 10 c1 condition code 9 c0 condition code 8 es error summary status 7 sf stack fault 6 exception flags pe precision error 5 ue underflow error 4 oe overflow error 3 ze zero divide error 2 de denormalized operation error 1 ie invalid operation error 0 tosp information 000 = fpr0 111 = f p r7
chapter 3 software environment 33 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information the fpu control word register allows a programmer to manage the fpu processing options. figure 13 shows the format of the fpu control word register. figure 13. fpu control word register the fpu tag word register contains information about the registers in the register stack. figure 14 shows the format of the fpu tag word register. figure 14. fpu tag word register 9876543210 10 11 12 13 14 15 p m o m p c r c i m z m u m d m rounding control information 00b = round to the nearest or even number 01b = round down toward negative infinity 10b = round up toward positive infinity 11b = truncate toward zero y precision control information 00b = 24 bits single precision real 01b = reserved 10b = 53 bits double precision real 11b = 64 bits extended precision real reserved symbol description bits y infinity bit (80287 compatibility) 12 rc rounding control 11C10 pc precision control 9C8 exception masks pm precision 5 um underflow 4 om overflow 3 zm zero divide 2 dm denormalized operation 1 im invalid operation 0 tag values 00 = valid 01 = zero 10 = special 11 = empty 87 65 43 2 1 0 10 11 12 13 14 15 tag (fpr7) tag (fpr6) tag (fpr4) tag (fpr5) tag (fpr2) tag (fpr3) tag (fpr0) tag (fpr1) 9
34 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information floating-point register data types floating-point registers use four different types of data packed decimal, single-precision real, double-precision real, and extended-precision real. figures 15 and 16 show the formats for these registers. figure 15. packed decimal data register figure 16. precision real data registers 0 79 precision 18 digits, 72 bits used, 4-bits/digit 71 s ignore or zero 78 72 description bits ignored on load, zeros on store 78-72 sign bit 79 0 63 double-precision real 31 0 single-precision real 0 79 22 s biased exponent 78 23 s biased exponent 63 64 51 52 biased exponent s significand significand significand 30 62 extended-precision real s = sign bit s = sign bit s = sign bit i 62 i = integer bit
chapter 3 software environment 35 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information mmx?/3dnow!? registers the AMD-K6-IIIE+ processor implements eight 64-bit mmx/3dnow! registers for use by multimedia software. these registers are mapped on the floating-point register stack. the mmx and 3dnow! instructions refer to these registers as mm0 to mm7. figure 17 shows the format of these registers. for more information, see the amd-k6 ? processor multimedia technology manual , order# 20726 and the 3dnow! technology manual, order# 21928. figure 17. mmx?/3dnow!? registers 63 0 mm0 mm7 mm1 mm6 mm5 mm2 mm3 mm4
36 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information mmx? technology data types for the mmx instructions, the mmx registers use three types of datapacked eight-byte integer, packed quadword integer, and packed dual doubleword integer. figure 18 on page 36 shows the format of these data types. figure 18. mmx? technology data types 63 0 packed bytes integer 63 0 packed words integer 63 0 packed doubleword integer 32 31 48 47 32 31 16 15 56 55 48 47 40 39 32 31 24 23 16 15 8 7 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 word 0 word 1 word 2 word 3 doubleword 1 doubleword 0
chapter 3 software environment 37 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 3dnow!? technology data types for 3dnow! instructions, the mmx/3dnow! registers use packed single-precision real data. figure 19 shows the format of the 3dnow! data type. figure 19. 3dnow!? technology data types 63 62 0 32 31 30 packed single precision floating point 55 54 23 22 biased exponent s significand s = sign bit biased exponent s significand s = sign bit
38 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information eflags register the eflags register provides for three different types of flagssystem, control, and status. the system flags provide operating system controls, the control flag provides directional information for string operations, and the status flags provide information resulting from logical and arithmetic operations. figure 20 shows the format of the eflags register. figure 20. eflags registers 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 i o p l 31 30 29 28 27 26 25 24 23 22 a f p f z f s f i f d f t f o f n t r f v m a c v i f v i p i d c f reserved symbol description bits id id flag 21 vip virtual interrupt pending 20 vif virtual interrupt flag 19 ac alignment check 18 vm virtual-8086 mode 17 rf resume flag 16 nt nested task 14 iopl i/o privilege level 13C12 of overflow flag 11 df direction flag 10 if interrupt flag 9 tf trap flag 8 sf sign flag 7 zf zero flag 6 af auxiliary flag 4 pf parity flag 2 cf carry flag 0
chapter 3 software environment 39 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information control registers the five control registers contain system control bits and pointers. figures 21 through 25 show the formats of the control registers. figure 21. control register 4 (cr4) figure 22. control register 3 (cr3) figure 23. control register 2 (cr2) 76543210 31 p s e t s d m c e v m e d e p v i reserved symbol description bit mce machine check enable 6 pse page size extensions 4 de debugging extensions 3 tsd time stamp disable 2 pvi protected virtual interrupts 1 vme virtual-8086 mode extensions 0 p c d 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 page directory base p w t reserved symbol description bit pcd page cache disable 4 pwt page writethrough 3 0 31 page fault linear address
40 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 24. control register 1 (cr1) figure 25. control register 0 (cr0) 0 31 reserved e t t s 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 a m e m w p m p p e n e p g c d n w reserved symbol description bit am alignment mask 18 wp write protect 16 ne numeric error 5 et extension type 4 ts task switched 3 em emulation 2 mp monitor coprocessor 1 pe protection enabled 0 symbol description bit pg paging 31 cd cache disable 30 nw not writethrough 29
chapter 3 software environment 41 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information debug registers figures 26 through 29 show the 32-bit debug registers supported by the processor. these registers are further described in debug on page 268. figure 26. debug register dr7 9876543210 10 11 12 13 14 15 l 2 l 1 l 3 g 3 g e l e l 0 g 0 g 1 g 2 g d 25 24 23 22 21 20 19 18 17 16 26 27 28 29 30 31 r/w 3 len 3 r/w 2 len 2 r/w 1 len 1 r/w 0 len 0 reserved symbol description bit gd general detect enabled 13 ge global exact breakpoint enabled 9 le local exact breakpoint enabled 8 g3 global exact breakpoint # 3 enabled 7 l3 local exact breakpoint # 3 enabled 6 g2 global exact breakpoint # 2 enabled 5 l2 local exact breakpoint # 2 enabled 4 g1 global exact breakpoint # 1 enabled 3 l1 local exact breakpoint # 1 enabled 2 g0 global exact breakpoint # 0 enabled 1 l0 local exact breakpoint # 0 enabled 0 symbol description bits len 3 length of breakpoint #3 31C30 r/w 3 type of transaction(s) to trap 29C28 len 2 length of breakpoint #2 27C26 r/w 2 type of transaction(s) to trap 25C24 len 1 length of breakpoint #1 23C22 r/w 1 type of transaction(s) to trap 21C20 len 0 length of breakpoint #0 19C18 r/w 0 type of transaction(s) to trap 17C16
42 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 27. debug register dr6 figure 28. debug registers dr5 and dr4 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 b 1 b 2 b s b 0 b t b d b 3 reserved symbol description bit bt breakpoint task switch 15 bs breakpoint single step 14 bd breakpoint debug access detected 13 b3 breakpoint #3 condition detected 3 b2 breakpoint #2 condition detected 2 b1 breakpoint #1 condition detected 1 b0 breakpoint #0 condition detected 0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr5 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr4
chapter 3 software environment 43 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 29. debug registers dr3, dr2, dr1, and dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 3 32-bit linear address dr3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 0 32-bit linear address dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 2 32-bit linear address dr2 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 1 32-bit linear address dr1
44 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 3.2 model-specific registers (msr) the AMD-K6-IIIE+ processor provides eleven model-specific registers (msrs) in the standard-power versions and twelve msrs in the low-power versions. n the value in the ecx register selects the msr to be addressed by the rdmsr and wrmsr instructions. n the values in eax and edx are used as inputs and outputs by the rdmsr and wrmsr instructions. table 5 lists the msrs and the corresponding value of the ecx register. figures 30 through 43 starting on page 45 show the msr formats. for more information about the msrs, see the embedded amd-k6? processors bios design guide application note , order# 23913. for more information about the rdmsr and wrmsr instructions, see the amd k86? family bios and software tools development guide , order# 21062. table 5. amd-k6?- iii e+ processor model-specific registers model-specific register value of ecx machine check address register (mcar) 00h machine check type register (mctr) 01h test register 12 (tr12) 0eh time stamp counter (tsc) 10h extended feature enable register (efer) c000_0080h syscall/sysret target address register (star) c000_0081h write handling control register (whcr) c000_0082h uc/wc cacheability control register (uwccr) c000_0085h processor state observability register (psor) c000_0087h page flush/invalidate register (pfir) c000_0088h level-2 cache array register (l2aar) c000_0089h enhanced power management register (epmr) 1 notes: 1. the epmr register is supported in the low-power versions only of the amd-k6- iii e+ processor. c000_0086h
chapter 3 software environment 45 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information machine check address register (mcar) and machine check type register (mctr) the AMD-K6-IIIE+ processor does not support the generation of a machine check exception. however, the processor does provide a 64-bit machine check address register (mcar), a 64-bit machine check type register (mctr), and a machine check enable (mce) bit in cr4. because the processor does not support machine check exceptions, the contents of the mcar and mctr are only affected by the wrmsr instruction and by reset being sampled asserted (where all bits in each register are reset to 0). the formats for the machine-check address register and the machine-check type register are shown in figure 30 and figure 31, respectively. the mcar register is msr 00h, and the mctr register is msr 01h. figure 30. machine-check address register (mcar) figure 31. machine-check type register (mctr) 0 63 mcar 54 0 63 mctr reserved
46 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information test register 12 (tr12) test register 12 provides a method for disabling the l1 caches. figure 32 shows the format of tr12. the tr12 register is msr 0eh. figure 32. test register 12 (tr12) time stamp counter with each processor clock cycle, the processor increments the 64-bit time stamp counter (tsc) msr. figure 33 shows the format of the tsc. the tsc register is msr 10h. the counter can be written or read using the wrmsr or rdmsr instructions when the ecx register contains the value 10h and cpl = 0. the counter can also be read using the rdtsc instruction, but the procedure must be executing at privilege level 0 for the rdtsc instruction to execute. this condition is reflected by the status of the time stamp disable (tsd) bit in cr4. with either of these instructions, the edx and eax registers hold the upper and lower dwords of the 64-bit value to be written to or read from the tsc, as follows: n edxupper 32 bits of tsc n eax lower 32 bits of tsc the tsc can be loaded with any arbitrary value. this feature is compatible with the pentium processor. figure 33. time stamp counter (tsc) 4210 63 c i 3 reserved symbol description bit ci cache inhibit bit 3 0 63 tsc
chapter 3 software environment 47 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information extended feature enable register (efer) the extended feature enable register (efer) contains the control bits that enable the extended features of the processor. figure 34 shows the format of the efer register, and table 6 defines the function of each bit of the efer register. the efer register is msr c000_0080h. figure 34. extended feature enable register (efer) for more information about the ewbec bits, see ewbe# control on page 229. table 6. extended feature enable register (efer) definition bit description r/w function 63C5 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 4 l2d r/w if l2d is set to 1, the l2 cache is completely disabled. this bit is provided for debug and testing purposes. for normal operation and maximum performance, this bit must be set to 0 (this is the default setting following reset). 3-2 ewbe control (ewbec) r/w this 2-bit field controls the behavior of the processor with respect to the ordering of write cycles and the ewbe# signal. efer[3] and efer[2] are global ewbe disable (gewbed) and speculative ewbe disable (sewbed), respectively. 1 data prefetch enable (dpe) r/w dpe must be set to 1 to enable data prefetching (this is the default setting following reset). if enabled, cache misses initiated by a memory read within a 32-byte line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 system call extension (sce) r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions. 10 63 s c e reserved 2 3 4 d p e ewbec symbol description bi t l2d l2 cache disable 4 ewbec ewbe# control 3-2 dpe data prefetch enable 1 sce system call extension 0 5 l 2 d
48 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information syscall/sysret target address register (star) the syscall/sysret target address register (star) contains the target eip address used by the syscall instruction and the 16-bit code and stack segment selector bases used by the syscall and sysret instructions. figure 35 shows the format of the star register, and table 7 defines the function of each bit of the star register. for more information, see the syscall and sysret instruction specification application note , order# 21086. the star register is msr c000_0081h. figure 35. syscall/sysret target address register (star) write handling control register (whcr) the write handling control register (whcr) is a msr that contains two fieldsthe write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 36). for more information, see write allocate on page 215. the whcr register is msr c000_0082h. figure 36. write handling control register (whcr) 31 0 63 target eip address 32 47 48 syscall cs selector and ss selector base sysret cs selector and ss selector base table 7. syscall/sysret target address register (star) definition bit description r/w 63C48 sysret cs and ss selector base r/w 47C32 syscall cs and ss selector base r/w 31C0 target eip address r/w 15 22 0 63 reserved waelim 16 note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits waelim write allocate enable limit 31-22 wae15m write allocate enable 15-to-16-mbyte 16 17 21 31 32
chapter 3 software environment 49 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information uc/wc cacheability control register (uwccr) the AMD-K6-IIIE+ processor provides two variable-range memory type range registers (mtrrs)mtrr0 and mtrr1that each specify a range of memory. each range can be defined as uncacheable (uc) or write-combining (wc) memory. for more information, see memory type range registers on page 231. the uwccr register is msr c000_0085h. . figure 37. uc/wc cacheability control register (uwccr) processor state observability register (psor) the AMD-K6-IIIE+ processor provides the processor state observability register (psor). the psor is defined as shown in figure 38 for all standard-power versions of the AMD-K6-IIIE+ processor. for a description of the psor register supported by the low-power versions of the processor, see page 148. the psor register is msr c000_0087h. . figure 38. processor state observability register (psor ) 16 0 63 physical address mask 0 17 31 physical base address 0 1 2 physical address mask 1 physical base address 1 32 33 34 48 49 u c 0 w c 0 u c 1 w c 1 mtrr1 mtrr0 symbol description bits uc0 uncacheable memory type 0 wc0 write-combining memory type 1 symbol description bits uc1 uncacheable memory type 32 wc1 write-combining memory type 33 20 63 bf reserved symbol description bit nol2 no l2 functionality 8 step processor stepping 7-4 bf bus frequency divisor 2-0 3 4 step 7 8 9 n o l 2
50 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information page flush/invalidate register (pfir) the AMD-K6-IIIE+ processor contains the page flush/invalidate register (pfir) (see figure 39) that allows cache invalidation and optional flushing of a specific 4-kbyte page from the linear address space. for more detailed information on pfir, see page flush/invalidate register (pfir) on page 223. the pfir register is msr c000_0088h. figure 39. page flush/invalidate register (pfir) level-2 cache array access register (l2aar) the AMD-K6-IIIE+ processor provides the l2aar register that allows for direct access to the l2 cache and l2 tag arrays. the l2aar register is msr c000_0089h. the operation that is performed on the l2 cache is a function of the instruction executedrdmsr or wrmsrand the contents of the edx register. the edx register specifies the location of the access, and whether the access is to the l2 cache data or tags (refer to figure 40). linpage 10 63 f / i reserved symbol description bit linpage 20-bit linear page address 31-12 pf page fault occurred 8 f/i flush/invalidate command 0 11 31 12 32 p f 987
chapter 3 software environment 51 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 40. l2 tag or data location for amd-k6?- iii e+ processoredx if the l2 cache data is read (as opposed to reading the tag information), the result (doubleword) is placed in eax in the format as illustrated in figure 41. similarly, if the l2 cache data is written, the write data is taken from eax. figure 41. l2 data eax if the l2 tag is read (as opposed to reading the cache data), the result is placed in eax in the format as illustrated in figure 42 on page 52. similarly, if the l2 tag is written, the write data is taken from eax. reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 15-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 0 31 data
52 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 42. l2 tag information for amd-k6?- iii e+ processoreax for more detailed information, refer to l2 cache and tag array testing on page 264. enhanced power management register (epmr) the AMD-K6-IIIE+ processor is designed with enhanced power management features, called amd powernow! technology, which include dynamic bus divisor control and dynamic core voltage control. the epmr register (see figure 43) defines the base address for a 16-byte block of i/o address space. enabling the epmr allows software to access the epm 16-byte i/o block, which contains bits for enabling, controlling, and monitoring the amd powernow! technology features. the epmr is msr c000_0086h. see amd powernow!? technology on page 143 for more information about the definition and use of this register. additional information can be found in the embedded amd-k6? processors bios design guide application note , order# 23913. c m d reserved 0 tag 15 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-15 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0
chapter 3 software environment 53 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 43. enhanced power management register (epmr) c m d reserved 0 16 63 15 4 31 2 e n g s b c iobase symbol descri p tion bi t iobase i/o base address 15-4 gsbc generate special bus cycle 1 en enable amd powernow! technology management 0
54 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 3.3 memory management registers the AMD-K6-IIIE+ processor controls segmented memory management with the registers listed in table 8. figure 44 shows the formats of these registers. figure 44. memory management registers table 8. memory management registers register name function global descriptor table register contains a pointer to the base of the global descriptor table interrupt descriptor table register contains a pointer to the base of the interrupt descriptor table local descriptor table register contains a pointer to the local descriptor table of the current task task register contains a pointer to the task state segment of the current task 15 0 16-bit limit 16 47 32-bit linear base address global and interrupt descriptor table registers 31 0 63 32-bit limit 32 32-bit linear base address 15 0 local descriptor table register and task register attributes 15 0 selector
chapter 3 software environment 55 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information task state segment figure 45 shows the format of the task state segment (tss). figure 45. task state segment (tss) 31 interrupt redirection bitmap (irb) (eight 32-bit locations) 0 i/o permission bitmap (iopb) (up to 8 kbytes) operating system data structure base address of iopb ldt selector 0000h 0000h 0000h 0000h 0000h 0000h 0000h gs fs ds ss cs es edi esi ebp esp ebx edx ecx eax cr3 eflags eip 0000h 0000h 0000h 0000h ss2 ss1 ss0 link (prior tss selector) esp0 esp1 esp2 tss limit from tr 64h 0 t 0000h
56 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 3.4 paging the AMD-K6-IIIE+ processor can physically address up to four gbytes of memory. this memory can be segmented into pages. the size of these pages is determined by the operating system design and the values set up in the page directory entries (pde) and page table entries (pte). the processor can access both 4-kbyte pages and 4-mbyte pages, and the page sizes can be intermixed within a page directory. when the page size extension (pse) bit in cr4 is set, the processor translates linear addresses using either the 4-kbyte translation lookaside buffer (tlb) or the 4-mbyte tlb, depending on the state of the page size (ps) bit in the page directory entry. figures 46 and figure 47 on page 57 show how 4-kbyte and 4-mbyte page translations work. figure 46. 4-kbyte paging mechanism linear address page directory page table 4-kbyte page frame cr3 0 11 12 21 31 22 page directory offset page table offset page offset pde pte physical address
chapter 3 software environment 57 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 47. 4-mbyte paging mechanism figures 48 through 50 starting on page 58 show the formats of the pde and pte. these entries contain information regarding the location of pages and their status. linear address page directory 4-mbyte page frame cr3 0 21 31 22 page directory offset page offset pde physical address
58 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 48. page directory entry 4-kbyte page table (pde) figure 49. page directory entry 4-mbyte page table (pde) 876543210 31 p c d u / s w / r 9 10 11 12 a v l 0 a p w t p page table base address symbol description bits avl available to software 11C9 reserved 8 ps page size 7 reserved 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0 876543210 31 p c d u / s w / r 9 10 11 12 a v l 1 a p w t p physical page base address reserved 21 22 symbol description bits avl available to software 11C9 reserved 8 ps page size 7 reserved 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0
chapter 3 software environment 59 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 50. page table entry (pte) 3.5 descriptors and gates there are various types of structures and registers in the x86 architecture that define, protect, and isolate code segments, data segments, task state segments, and gates. these structures are called descriptors. n the application segment descriptor is used to point to either a data or code segment. figure 51 on page 60 shows the application segment descriptor format. table 9 on page 60 contains information describing the memory segment type to which the descriptor points. n the system segment descriptor is used to point to a task state segment, a call gate, or a local descriptor table. figure 52 on page 61 shows the system segment descriptor format. table 10 on page 61 contains information describing the type of segment or gate to which the descriptor points. n the AMD-K6-IIIE+ processor uses gates to transfer control between executable segments with different privilege levels. figure 53 on page 62 shows the format of the gate descriptor types. table 10 on page 61 contains information describing the type of segment or gate to which the descriptor points. 876543210 31 p c d u / s w / r 9 10 11 12 a v l a p w t p physical page base address d symbol description bits avl available to software 11C9 reserved 8C7 d dirty 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0
60 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 51. application segment descriptor base address 15C0 segment limit 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 segment limit p dpl 1 type a v l g d base address 31C24 base address 23C16 reserved symbol description bits g granularity 23 d 32-bit/16-bit 22 avl available to software 20 p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 9 11-8 table 9. application segment types type data/code description 0 data read-only 1 read-onlyaccessed 2 read/write 3 read/writeaccessed 4 read-onlyexpand-down 5 read-onlyexpand-down, accessed 6 read/writeexpand-down 7 read/writeexpand-down, accessed 8 code execute-only 9 execute-onlyaccessed a execute/read b execute/readaccessed c execute-onlyconforming d execute-onlyconforming, accessed e execute/read-onlyconforming f execute/read-onlyconforming, accessed
chapter 3 software environment 61 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 52. system segment descriptor base address 15C0 segment limit 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 segment limit p dpl 0 type a v l g x base address 31C24 base address 23C16 reserved symbol description bits g granularity 23 x not needed 22 avl availability to software 20 p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 10 11-8 table 10. system segment and gate types type description 0 reserved 1 available 16-bit tss 2ldt 3busy 16-bit tss 4 16-bit call gate 5task gate 6 16-bit interrupt gate 7 16-bit trap gate 8 reserved 9 available 32-bit tss a reserved b busy 32-bit tss c 32-bit call gate d reserved e 32-bit interrupt gate f 32-bit trap gate
62 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 53. gate descriptor 3.6 exceptions and interrupts table 11 summarizes the exceptions and interrupts. dpl 0 type offset 31C16 p segment selector offset 15C0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved symbol description bits p present/valid bit 15 dpl descriptor privilege level 14-13 dt descriptor type 12 type see table 10 on page 61 11-8 table 11. summary of exceptions and interrupts interrupt number interrupt type cause 0 divide by zero error div, idiv 1 debug debug trap or fault 2 non-maskable interrupt nmi signal sampled asserted 3 breakpoint int 3 4 overflow into 5 bounds check bound 6 invalid opcode invalid instruction 7 device not available esc and wait 8 double fault fault occurs while handling a fault 9 reserved - interrupt 13 10 invalid tss task switch to an invalid segment 11 segment not present instruction loads a segment and present bit is 0 (invalid segment) 12 stack segment stack operation causes limit violation or present bit is 0 13 general protection segment related or miscellaneous invalid actions 14 page fault page protection violation or a reference to missing page 16 floating-point error arithmetic error generated by floating-point instruction 17 alignment check data reference to an unaligned operand. (the ac flag and the am bit of cr0 are set to 1.) 0C255 software interrupt int n
chapter 3 software environment 63 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 3.7 instructions supported by the amd-k6?- iii e+ processor this section documents all of the x86 instructions supported by the AMD-K6-IIIE+ processor. tables 12 through 16 starting on page 65 define the integer, floating-point, mmx, 3dnow! technology instructions, and 3dnow! technology digital signal processing (dsp) extensions for the AMD-K6-IIIE+ processor, respectively. for details about the mmx instructions, 3dnow! technology instructions, and 3dnow! technology dsp extensions refer to the following manuals: n mmx instructions amd-k6 ? processor multimedia technology manual , order# 20726 n 3dnow! technology instructions 3dnow! technology manual , order# 21928 n 3dnow! technology dsp extensions amd extensions to the 3dnow! and mmx instruction set manual , order# 22466 each table shows the instruction mnemonic, opcode, modr/m byte, decode type, and risc86 operation(s) for each instruction. instruction mnemonic and operand types the first column in these tables indicates the instruction mnemonic and operand types with the following notations: n disp16/32 16-bit or 32-bit displacement value n disp32/48 doubleword or 48-bit displacement value n disp8 8-bit displacement value n exx register width depending on the operand size n imm16/32 16-bit or 32-bit immediate value n imm8 8-bit immediate value n mem16/32 word or doubleword integer value in memory n mem32/48 doubleword or 48-bit integer value in memory n mem32real 32-bit floating-point value in memory n mem48 48-bit integer value in memory n mem64 64-bit integer value in memory n mem64real 64-bit floating-point value in memory n mem8 byte integer value in memory n mem80real 80-bit floating-point value in memory n mmreg mmx/3dnow! register
64 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information n mmreg1 mmx/3dnow! register defined by bits 5, 4, and 3 of the modr/m byte n mmreg2 mmx/3dnow! register defined by bits 2, 1, and 0 of the modr/m byte n mreg16/32 word or doubleword integer register, or word or doubleword integer value in memory defined by the modr/m byte n mreg8 byte integer register or byte integer value in memory defined by the modr/m byte n reg8 byte integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modr/m byte n reg16/32 word or doubleword integer register defined by instruction byte(s) or bits 5, 4, and 3 of the modr/m byte opcode bytes the second and third columns list all applicable opcode bytes. modr/m byte the fourth column lists the modr/m byte when used by the instruction. the modr/m byte defines the instruction as a register or memory form. if modr/m bits 7 and 6 are documented as mm (memory form), mm can only be 10b, 01b or 00b. decode type the fifth column lists the type of instruction decodeshort, long, and vector. the AMD-K6-IIIE+ processor decode logic can process two short, one long, or one vector decode per clock. risc86? operation the sixth column lists the type of risc86 operation(s) required for the instruction. the operation types and corresponding execution units are as follows: n alu either of the integer execution units n alux integer x execution unit only n branch branch condition unit n float floating-point execution unit n limm load immediate, instruction control unit n load, fload, mload load unit n meu multimedia execution units for mmx and 3dnow! instructions n store, fstore, mstore store unit
chapter 3 software environment 65 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 12. integer instructions instruction mnemonic first byte second byte modr/m byte decode type risc86 operations aaa 37h vector aad d5h 0ah vector aam d4h 0ah vector aas 3fh vector adc mreg8, reg8 10h 11-xxx-xxx vector adc mem8, reg8 10h mm-xxx-xxx vector adc mreg16/32, reg16/32 11h 11-xxx-xxx vector adc mem16/32, reg16/32 11h mm-xxx-xxx vector adc reg8, mreg8 12h 11-xxx-xxx vector adc reg8, mem8 12h mm-xxx-xxx vector adc reg16/32, mreg16/32 13h 11-xxx-xxx vector adc reg16/32, mem16/32 13h mm-xxx-xxx vector adc al, imm8 14h vector adc eax, imm16/32 15h vector adc mreg8, imm8 80h 11-010-xxx vector adc mem8, imm8 80h mm-010-xxx vector adc mreg16/32, imm16/32 81h 11-010-xxx vector adc mem16/32, imm16/32 81h mm-010-xxx vector adc mreg16/32, imm8 (signed ext.) 83h 11-010-xxx vector adc mem16/32, imm8 (signed ext.) 83h mm-010-xxx vector add mreg8, reg8 00h 11-xxx-xxx short alux add mem8, reg8 00h mm-xxx-xxx long load, alux, store add mreg16/32, reg16/32 01h 11-xxx-xxx short alu add mem16/32, reg16/32 01h mm-xxx-xxx long load, alu, store add reg8, mreg8 02h 11-xxx-xxx short alux add reg8, mem8 02h mm-xxx-xxx short load, alux add reg16/32, mreg16/32 03h 11-xxx-xxx short alu add reg16/32, mem16/32 03h mm-xxx-xxx short load, alu add al, imm8 04h short alux add eax, imm16/32 05h short alu add mreg8, imm8 80h 11-000-xxx short alux add mem8, imm8 80h mm-000-xxx long load, alux, store add mreg16/32, imm16/32 81h 11-000-xxx short alu add mem16/32, imm16/32 81h mm-000-xxx long load, alu, store add mreg16/32, imm8 (signed ext.) 83h 11-000-xxx short alux
66 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information add mem16/32, imm8 (signed ext.) 83h mm-000-xxx long load, alux, store and mreg8, reg8 20h 11-xxx-xxx short alux and mem8, reg8 20h mm-xxx-xxx long load, alux, store and mreg16/32, reg16/32 21h 11-xxx-xxx short alu and mem16/32, reg16/32 21h mm-xxx-xxx long load, alu, store and reg8, mreg8 22h 11-xxx-xxx short alux and reg8, mem8 22h mm-xxx-xxx short load, alux and reg16/32, mreg16/32 23h 11-xxx-xxx short alu and reg16/32, mem16/32 23h mm-xxx-xxx short load, alu and al, imm8 24h short alux and eax, imm16/32 25h short alu and mreg8, imm8 80h 11-100-xxx short alux and mem8, imm8 80h mm-100-xxx long load, alux, store and mreg16/32, imm16/32 81h 11-100-xxx short alu and mem16/32, imm16/32 81h mm-100-xxx long load, alu, store and mreg16/32, imm8 (signed ext.) 83h 11-100-xxx short alux and mem16/32, imm8 (signed ext.) 83h mm-100-xxx long load, alux, store arpl mreg16, reg16 63h 11-xxx-xxx vector arpl mem16, reg16 63h mm-xxx-xxx vector bound 62h vector bsf reg16/32, mreg16/32 0fh bch 11-xxx-xxx vector bsf reg16/32, mem16/32 0fh bch mm-xxx-xxx vector bsr reg16/32, mreg16/32 0fh bdh 11-xxx-xxx vector bsr reg16/32, mem16/32 0fh bdh mm-xxx-xxx vector bswap eax 0fh c8h long alu bswap ecx 0fh c9h long alu bswap edx 0fh cah long alu bswap ebx 0fh cbh long alu bswap esp 0fh cch long alu bswap ebp 0fh cdh long alu bswap esi 0fh ceh long alu bswap edi 0fh cfh long alu bt mreg16/32, reg16/32 0fh a3h 11-xxx-xxx vector bt mem16/32, reg16/32 0fh a3h mm-xxx-xxx vector bt mreg16/32, imm8 0fh bah 11-100-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 67 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information bt mem16/32, imm8 0fh bah mm-100-xxx vector btc mreg16/32, reg16/32 0fh bbh 11-xxx-xxx vector btc mem16/32, reg16/32 0fh bbh mm-xxx-xxx vector btc mreg16/32, imm8 0fh bah 11-111-xxx vector btc mem16/32, imm8 0fh bah mm-111-xxx vector btr mreg16/32, reg16/32 0fh b3h 11-xxx-xxx vector btr mem16/32, reg16/32 0fh b3h mm-xxx-xxx vector btr mreg16/32, imm8 0fh bah 11-110-xxx vector btr mem16/32, imm8 0fh bah mm-110-xxx vector bts mreg16/32, reg16/32 0fh abh 11-xxx-xxx vector bts mem16/32, reg16/32 0fh abh mm-xxx-xxx vector bts mreg16/32, imm8 0fh bah 11-101-xxx vector bts mem16/32, imm8 0fh bah mm-101-xxx vector call full pointer 9ah vector call near imm16/32 e8h short store call mem16:16/32 ffh 11-011-xxx vector call near mreg32 (indirect) ffh 11-010-xxx vector call near mem32 (indirect) ffh mm-010-xxx vector cbw/cwde eax 98h vector clc f8h vector cld fch vector cli fah vector clts 0fh 06h vector cmc f5h vector cmp mreg8, reg8 38h 11-xxx-xxx short alux cmp mem8, reg8 38h mm-xxx-xxx short load, alux cmp mreg16/32, reg16/32 39h 11-xxx-xxx short alu cmp mem16/32, reg16/32 39h mm-xxx-xxx short load, alu cmp reg8, mreg8 3ah 11-xxx-xxx short alux cmp reg8, mem8 3ah mm-xxx-xxx short load, alux cmp reg16/32, mreg16/32 3bh 11-xxx-xxx short alu cmp reg16/32, mem16/32 3bh mm-xxx-xxx short load, alu cmp al, imm8 3ch short alux cmp eax, imm16/32 3dh short alu cmp mreg8, imm8 80h 11-111-xxx short alux table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
68 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information cmp mem8, imm8 80h mm-111-xxx short load, alux cmp mreg16/32, imm16/32 81h 11-111-xxx short alu cmp mem16/32, imm16/32 81h mm-111-xxx short load, alu cmp mreg16/32, imm8 (signed ext.) 83h 11-111-xxx long load, alu cmp mem16/32, imm8 (signed ext.) 83h mm-111-xxx long load, alu cmpsb mem8, mem8 a6h vector cmpsw mem16, mem32 a7h vector cmpsd mem32, mem32 a7h vector cmpxchg mreg8, reg8 0fh b0h 11-xxx-xxx vector cmpxchg mem8, reg8 0fh b0h mm-xxx-xxx vector cmpxchg mreg16/32, reg16/32 0fh b1h 11-xxx-xxx vector cmpxchg mem16/32, reg16/32 0fh b1h mm-xxx-xxx vector cmpxchg8b edx:eax 0fh c7h 11-xxx-xxx vector cmpxchg8b mem64 0fh c7h mm-xxx-xxx vector cpuid 0fh a2h vector cwd/cdq edx, eax 99h vector daa 27h vector das 2fh vector dec eax 48h short alu dec ecx 49h short alu dec edx 4ah short alu dec ebx 4bh short alu dec esp 4ch short alu dec ebp 4dh short alu dec esi 4eh short alu dec edi 4fh short alu dec mreg8 feh 11-001-xxx vector dec mem8 feh mm-001-xxx long load, alux, store dec mreg16/32 ffh 11-001-xxx vector dec mem16/32 ffh mm-001-xxx long load, alu, store div al, mreg8 f6h 11-110-xxx vector div al, mem8 f6h mm-110-xxx vector div eax, mreg16/32 f7h 11-110-xxx vector div eax, mem16/32 f7h mm-110-xxx vector idiv mreg8 f6h 11-111-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 69 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information idiv mem8 f6h mm-111-xxx vector idiv eax, mreg16/32 f7h 11-111-xxx vector idiv eax, mem16/32 f7h mm-111-xxx vector imul reg16/32, imm16/32 69h 11-xxx-xxx vector imul reg16/32, mreg16/32, imm16/32 69h 11-xxx-xxx vector imul reg16/32, mem16/32, imm16/32 69h mm-xxx-xxx vector imul reg16/32, imm8 (sign extended) 6bh 11-xxx-xxx vector imul reg16/32, mreg16/32, imm8 (signed) 6bh 11-xxx-xxx vector imul reg16/32, mem16/32, imm8 (signed) 6bh mm-xxx-xxx vector imul ax, al, mreg8 f6h 11-101-xxx vector imul ax, al, mem8 f6h mm-101-xxx vector imul edx:eax, eax, mreg16/32 f7h 11-101-xxx vector imul edx:eax, eax, mem16/32 f7h mm-101-xxx vector imul reg16/32, mreg16/32 0fh afh 11-xxx-xxx vector imul reg16/32, mem16/32 0fh afh mm-xxx-xxx vector in al, imm8 e4h vector in ax, imm8 e5h vector in eax, imm8 e5h vector in al, dx ech vector in ax, dx edh vector in eax, dx edh vector inc eax 40h short alu inc ecx 41h short alu inc edx 42h short alu inc ebx 43h short alu inc esp 44h short alu inc ebp 45h short alu inc esi 46h short alu inc edi 47h short alu inc mreg8 feh 11-000-xxx vector inc mem8 feh mm-000-xxx long load, alux, store inc mreg16/32 ffh 11-000-xxx vector inc mem16/32 ffh mm-000-xxx long load, alu, store invd 0fh 08h vector invlpg 0fh 01h mm-111-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
70 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information jo short disp8 70h short branch jb/jnae short disp8 71h short branch jno short disp8 71h short branch jnb/jae short disp8 73h short branch jz/je short disp8 74h short branch jnz/jne short disp8 75h short branch jbe/jna short disp8 76h short branch jnbe/ja short disp8 77h short branch js short disp8 78h short branch jns short disp8 79h short branch jp/jpe short disp8 7ah short branch jnp/jpo short disp8 7bh short branch jl/jnge short disp8 7ch short branch jnl/jge short disp8 7dh short branch jle/jng short disp8 7eh short branch jnle/jg short disp8 7fh short branch jcxz/jec short disp8 e3h vector jo near disp16/32 0fh 80h short branch jno near disp16/32 0fh 81h short branch jb/jnae near disp16/32 0fh 82h short branch jnb/jae near disp16/32 0fh 83h short branch jz/je near disp16/32 0fh 84h short branch jnz/jne near disp16/32 0fh 85h short branch jbe/jna near disp16/32 0fh 86h short branch jnbe/ja near disp16/32 0fh 87h short branch js near disp16/32 0fh 88h short branch jns near disp16/32 0fh 89h short branch jp/jpe near disp16/32 0fh 8ah short branch jnp/jpo near disp16/32 0fh 8bh short branch jl/jnge near disp16/32 0fh 8ch short branch jnl/jge near disp16/32 0fh 8dh short branch jle/jng near disp16/32 0fh 8eh short branch jnle/jg near disp16/32 0fh 8fh short branch jmp near disp16/32 (direct) e9h short branch jmp far disp32/48 (direct) eah vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 71 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information jmp disp8 (short) ebh short branch jmp far mreg32 (indirect) efh 11-101-xxx vector jmp far mem32 (indirect) efh mm-101-xxx vector jmp near mreg16/32 (indirect) ffh 11-100-xxx vector jmp near mem16/32 (indirect) ffh mm-100-xxx vector lahf 9fh vector lar reg16/32, mreg16/32 0fh 02h 11-xxx-xxx vector lar reg16/32, mem16/32 0fh 02h mm-xxx-xxx vector lds reg16/32, mem32/48 c5h mm-xxx-xxx vector lea reg16/32, mem16/32 8dh mm-xxx-xxx short load, alu leave c9h long load, alu, alu les reg16/32, mem32/48 c4h mm-xxx-xxx vector lfs reg16/32, mem32/48 0fh b4h vector lgdt mem48 0fh 01h mm-010-xxx vector lgs reg16/32, mem32/48 0fh b5h vector lidt mem48 0fh 01h mm-011-xxx vector lldt mreg16 0fh 00h 11-010-xxx vector lldt mem16 0fh 00h mm-010-xxx vector lmsw mreg16 0fh 01h 11-100-xxx vector lmsw mem16 0fh 01h mm-100-xxx vector lodsb al, mem8 ach long load, alu lodsw ax, mem16 adh long load, alu lodsd eax, mem32 adh long load, alu loop disp8 e2h short alu, branch loope/loopz disp8 e1h vector loopne/loopnz disp8 e0h vector lsl reg16/32, mreg16/32 0fh 03h 11-xxx-xxx vector lsl reg16/32, mem16/32 0fh 03h mm-xxx-xxx vector lss reg16/32, mem32/48 0fh b2h mm-xxx-xxx vector ltr mreg16 0fh 00h 11-011-xxx vector ltr mem16 0fh 00h mm-011-xxx vector mov mreg8, reg8 88h 11-xxx-xxx short alux mov mem8, reg8 88h mm-xxx-xxx short store mov mreg16/32, reg16/32 89h 11-xxx-xxx short alu mov mem16/32, reg16/32 89h mm-xxx-xxx short store table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
72 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information mov reg8, mreg8 8ah 11-xxx-xxx short alux mov reg8, mem8 8ah mm-xxx-xxx short load mov reg16/32, mreg16/32 8bh 11-xxx-xxx short alu mov reg16/32, mem16/32 8bh mm-xxx-xxx short load mov mreg16, segment reg 8ch 11-xxx-xxx long load mov mem16, segment reg 8ch mm-xxx-xxx vector mov segment reg, mreg16 8eh 11-xxx-xxx vector mov segment reg, mem16 8eh mm-xxx-xxx vector mov al, mem8 a0h short load mov eax, mem16/32 a1h short load mov mem8, al a2h short store mov mem16/32, eax a3h short store mov al, imm8 b0h short limm mov cl, imm8 b1h short limm mov dl, imm8 b2h short limm mov bl, imm8 b3h short limm mov ah, imm8 b4h short limm mov ch, imm8 b5h short limm mov dh, imm8 b6h short limm mov bh, imm8 b7h short limm mov eax, imm16/32 b8h short limm mov ecx, imm16/32 b9h short limm mov edx, imm16/32 bah short limm mov ebx, imm16/32 bbh short limm mov esp, imm16/32 bch short limm mov ebp, imm16/32 bdh short limm mov esi, imm16/32 beh short limm mov edi, imm16/32 bfh short limm mov mreg8, imm8 c6h 11-000-xxx short limm mov mem8, imm8 c6h mm-000-xxx long store mov mreg16/32, imm16/32 c7h 11-000-xxx short limm mov mem16/32, imm16/32 c7h mm-000-xxx long store mov reg32, cr0 0fh 20h 11-000-xxx vector mov reg32, cr2 0fh 20h 11-010-xxx vector mov reg32, cr3 0fh 20h 11-011-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 73 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information mov reg32, cr4 0fh 20h 11-100-xxx vector mov cr0, reg32 0fh 22h 11-000-xxx vector mov cr2, reg32 0fh 22h 11-010-xxx vector mov cr3, reg32 0fh 22h 11-011-xxx vector mov cr4, reg32 0fh 22h 11-100-xxx vector movsb mem8,mem8 a4h long load, store, alux, alux movsd mem16, mem16 a5h long load, store, alu, alu movsw mem32, mem32 a5h long load, store, alu, alu movsx reg16/32, mreg8 0fh beh 11-xxx-xxx short alu movsx reg16/32, mem8 0fh beh mm-xxx-xxx short load, alu movsx reg32, mreg16 0fh bfh 11-xxx-xxx short alu movsx reg32, mem16 0fh bfh mm-xxx-xxx short load, alu movzx reg16/32, mreg8 0fh b6h 11-xxx-xxx short alu movzx reg16/32, mem8 0fh b6h mm-xxx-xxx short load, alu movzx reg32, mreg16 0fh b7h 11-xxx-xxx short alu movzx reg32, mem16 0fh b7h mm-xxx-xxx short load, alu mul al, mreg8 f6h 11-100-xxx vector mul al, mem8 f6h mm-100-xxx vector mul eax, mreg16/32 f7h 11-100-xxx vector mul eax, mem16/32 f7h mm-100-xxx vector neg mreg8 f6h 11-011-xxx short alux neg mem8 f6h mm-011-xxx vector neg mreg16/32 f7h 11-011-xxx short alu neg mem16/32 f7h mm-011-xxx vector nop (xchg eax, eax) 90h short limm not mreg8 f6h 11-010-xxx short alux not mem8 f6h mm-010-xxx vector not mreg16/32 f7h 11-010-xxx short alu not mem16/32 f7h mm-010-xxx vector or mreg8, reg8 08h 11-xxx-xxx short alux or mem8, reg8 08h mm-xxx-xxx long load, alux, store or mreg16/32, reg16/32 09h 11-xxx-xxx short alu or mem16/32, reg16/32 09h mm-xxx-xxx long load, alu, store or reg8, mreg8 0ah 11-xxx-xxx short alux or reg8, mem8 0ah mm-xxx-xxx short load, alux table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
74 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information or reg16/32, mreg16/32 0bh 11-xxx-xxx short alu or reg16/32, mem16/32 0bh mm-xxx-xxx short load, alu or al, imm8 0ch short alux or eax, imm16/32 0dh short alu or mreg8, imm8 80h 11-001-xxx short alux or mem8, imm8 80h mm-001-xxx long load, alux, store or mreg16/32, imm16/32 81h 11-001-xxx short alu or mem16/32, imm16/32 81h mm-001-xxx long load, alu, store or mreg16/32, imm8 (signed ext.) 83h 11-001-xxx short alux or mem16/32, imm8 (signed ext.) 83h mm-001-xxx long load, alux, store out imm8, al e6h vector out imm8, ax e7h vector out imm8, eax e7h vector out dx, al eeh vector out dx, ax efh vector out dx, eax efh vector pop es 07h vector pop ss 17h vector pop ds 1fh vector pop fs 0fh a1h vector pop gs 0fh a9h vector pop eax 58h short load, alu pop ecx 59h short load, alu pop edx 5ah short load, alu pop ebx 5bh short load, alu pop esp 5ch short load, alu pop ebp 5dh short load, alu pop esi 5eh short load, alu pop edi 5fh short load, alu pop mreg 16/32 8fh 11-000-xxx short load, alu pop mem 16/32 8fh mm-000-xxx long load, store, alu popa/popad 61h vector popf/popfd 9dh vector push es 06h long load, store push cs 0eh vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 75 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information push fs 0fh a0h vector push gs 0fh a8h vector push ss 16h vector push ds 1eh long load, store push eax 50h short store push ecx 51h short store push edx 52h short store push ebx 53h short store push esp 54h short store push ebp 55h short store push esi 56h short store push edi 57h short store push imm8 6ah long store push imm16/32 68h long store push mreg16/32 ffh 11-110-xxx vector push mem16/32 ffh mm-110-xxx long load, store pusha/pushad 60h vector pushf/pushfd 9ch vector rcl mreg8, imm8 c0h 11-010-xxx vector rcl mem8, imm8 c0h mm-010-xxx vector rcl mreg16/32, imm8 c1h 11-010-xxx vector rcl mem16/32, imm8 c1h mm-010-xxx vector rcl mreg8, 1 d0h 11-010-xxx vector rcl mem8, 1 d0h mm-010-xxx vector rcl mreg16/32, 1 d1h 11-010-xxx vector rcl mem16/32, 1 d1h mm-010-xxx vector rcl mreg8, cl d2h 11-010-xxx vector rcl mem8, cl d2h mm-010-xxx vector rcl mreg16/32, cl d3h 11-010-xxx vector rcl mem16/32, cl d3h mm-010-xxx vector rcr mreg8, imm8 c0h 11-011-xxx vector rcr mem8, imm8 c0h mm-011-xxx vector rcr mreg16/32, imm8 c1h 11-011-xxx vector rcr mem16/32, imm8 c1h mm-011-xxx vector rcr mreg8, 1 d0h 11-011-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
76 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information rcr mem8, 1 d0h mm-011-xxx vector rcr mreg16/32, 1 d1h 11-011-xxx vector rcr mem16/32, 1 d1h mm-011-xxx vector rcr mreg8, cl d2h 11-011-xxx vector rcr mem8, cl d2h mm-011-xxx vector rcr mreg16/32, cl d3h 11-011-xxx vector rcr mem16/32, cl d3h mm-011-xxx vector rdmsr 0fh 32h vector rdtsc 0fh 31h vector ret near imm16 c2h vector ret near c3h vector ret far imm16 cah vector ret far cbh vector rol mreg8, imm8 c0h 11-000-xxx vector rol mem8, imm8 c0h mm-000-xxx vector rol mreg16/32, imm8 c1h 11-000-xxx vector rol mem16/32, imm8 c1h mm-000-xxx vector rol mreg8, 1 d0h 11-000-xxx vector rol mem8, 1 d0h mm-000-xxx vector rol mreg16/32, 1 d1h 11-000-xxx vector rol mem16/32, 1 d1h mm-000-xxx vector rol mreg8, cl d2h 11-000-xxx vector rol mem8, cl d2h mm-000-xxx vector rol mreg16/32, cl d3h 11-000-xxx vector rol mem16/32, cl d3h mm-000-xxx vector ror mreg8, imm8 c0h 11-001-xxx vector ror mem8, imm8 c0h mm-001-xxx vector ror mreg16/32, imm8 c1h 11-001-xxx vector ror mem16/32, imm8 c1h mm-001-xxx vector ror mreg8, 1 d0h 11-001-xxx vector ror mem8, 1 d0h mm-001-xxx vector ror mreg16/32, 1 d1h 11-001-xxx vector ror mem16/32, 1 d1h mm-001-xxx vector ror mreg8, cl d2h 11-001-xxx vector ror mem8, cl d2h mm-001-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 77 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information ror mreg16/32, cl d3h 11-001-xxx vector ror mem16/32, cl d3h mm-001-xxx vector rsm 0fh aah vector sahf 9eh vector sar mreg8, imm8 c0h 11-111-xxx short alux sar mem8, imm8 c0h mm-111-xxx vector sar mreg16/32, imm8 c1h 11-111-xxx short alu sar mem16/32, imm8 c1h mm-111-xxx vector sar mreg8, 1 d0h 11-111-xxx short alux sar mem8, 1 d0h mm-111-xxx vector sar mreg16/32, 1 d1h 11-111-xxx short alu sar mem16/32, 1 d1h mm-111-xxx vector sar mreg8, cl d2h 11-111-xxx short alux sar mem8, cl d2h mm-111-xxx vector sar mreg16/32, cl d3h 11-111-xxx short alu sar mem16/32, cl d3h mm-111-xxx vector sbb mreg8, reg8 18h 11-xxx-xxx vector sbb mem8, reg8 18h mm-xxx-xxx vector sbb mreg16/32, reg16/32 19h 11-xxx-xxx vector sbb mem16/32, reg16/32 19h mm-xxx-xxx vector sbb reg8, mreg8 1ah 11-xxx-xxx vector sbb reg8, mem8 1ah mm-xxx-xxx vector sbb reg16/32, mreg16/32 1bh 11-xxx-xxx vector sbb reg16/32, mem16/32 1bh mm-xxx-xxx vector sbb al, imm8 1ch vector sbb eax, imm16/32 1dh vector sbb mreg8, imm8 80h 11-011-xxx vector sbb mem8, imm8 80h mm-011-xxx vector sbb mreg16/32, imm16/32 81h 11-011-xxx vector sbb mem16/32, imm16/32 81h mm-011-xxx vector sbb mreg16/32, imm8 (signed ext.) 83h 11-011-xxx vector sbb mem16/32, imm8 (signed ext.) 83h mm-011-xxx vector scasb al, mem8 aeh vector scasw ax, mem16 afh vector scasd eax, mem32 afh vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
78 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information seto mreg8 0fh 90h 11-xxx-xxx vector seto mem8 0fh 90h mm-xxx-xxx vector setno mreg8 0fh 91h 11-xxx-xxx vector setno mem8 0fh 91h mm-xxx-xxx vector setb/setnae mreg8 0fh 92h 11-xxx-xxx vector setb/setnae mem8 0fh 92h mm-xxx-xxx vector setnb/setae mreg8 0fh 93h 11-xxx-xxx vector setnb/setae mem8 0fh 93h mm-xxx-xxx vector setz/sete mreg8 0fh 94h 11-xxx-xxx vector setz/sete mem8 0fh 94h mm-xxx-xxx vector setnz/setne mreg8 0fh 95h 11-xxx-xxx vector setnz/setne mem8 0fh 95h mm-xxx-xxx vector setbe/setna mreg8 0fh 96h 11-xxx-xxx vector setbe/setna mem8 0fh 96h mm-xxx-xxx vector setnbe/seta mreg8 0fh 97h 11-xxx-xxx vector setnbe/seta mem8 0fh 97h mm-xxx-xxx vector sets mreg8 0fh 98h 11-xxx-xxx vector sets mem8 0fh 98h mm-xxx-xxx vector setns mreg8 0fh 99h 11-xxx-xxx vector setns mem8 0fh 99h mm-xxx-xxx vector setp/setpe mreg8 0fh 9ah 11-xxx-xxx vector setp/setpe mem8 0fh 9ah mm-xxx-xxx vector setnp/setpo mreg8 0fh 9bh 11-xxx-xxx vector setnp/setpo mem8 0fh 9bh mm-xxx-xxx vector setl/setnge mreg8 0fh 9ch 11-xxx-xxx vector setl/setnge mem8 0fh 9ch mm-xxx-xxx vector setnl/setge mreg8 0fh 9dh 11-xxx-xxx vector setnl/setge mem8 0fh 9dh mm-xxx-xxx vector setle/setng mreg8 0fh 9eh 11-xxx-xxx vector setle/setng mem8 0fh 9eh mm-xxx-xxx vector setnle/setg mreg8 0fh 9fh 11-xxx-xxx vector setnle/setg mem8 0fh 9fh mm-xxx-xxx vector sgdt mem48 0fh 01h mm-000-xxx vector sidt mem48 0fh 01h mm-001-xxx vector shl/sal mreg8, imm8 c0h 11-100-xxx short alux table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 79 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information shl/sal mem8, imm8 c0h mm-100-xxx vector shl/sal mreg16/32, imm8 c1h 11-100-xxx short alu shl/sal mem16/32, imm8 c1h mm-100-xxx vector shl/sal mreg8, 1 d0h 11-100-xxx short alux shl/sal mem8, 1 d0h mm-100-xxx vector shl/sal mreg16/32, 1 d1h 11-100-xxx short alu shl/sal mem16/32, 1 d1h mm-100-xxx vector shl/sal mreg8, cl d2h 11-100-xxx short alux shl/sal mem8, cl d2h mm-100-xxx vector shl/sal mreg16/32, cl d3h 11-100-xxx short alu shl/sal mem16/32, cl d3h mm-100-xxx vector shr mreg8, imm8 c0h 11-101-xxx short alux shr mem8, imm8 c0h mm-101-xxx vector shr mreg16/32, imm8 c1h 11-101-xxx short alu shr mem16/32, imm8 c1h mm-101-xxx vector shr mreg8, 1 d0h 11-101-xxx short alux shr mem8, 1 d0h mm-101-xxx vector shr mreg16/32, 1 d1h 11-101-xxx short alu shr mem16/32, 1 d1h mm-101-xxx vector shr mreg8, cl d2h 11-101-xxx short alux shr mem8, cl d2h mm-101-xxx vector shr mreg16/32, cl d3h 11-101-xxx short alu shr mem16/32, cl d3h mm-101-xxx vector shld mreg16/32, reg16/32, imm8 0fh a4h 11-xxx-xxx vector shld mem16/32, reg16/32, imm8 0fh a4h mm-xxx-xxx vector shld mreg16/32, reg16/32, cl 0fh a5h 11-xxx-xxx vector shld mem16/32, reg16/32, cl 0fh a5h mm-xxx-xxx vector shrd mreg16/32, reg16/32, imm8 0fh ach 11-xxx-xxx vector shrd mem16/32, reg16/32, imm8 0fh ach mm-xxx-xxx vector shrd mreg16/32, reg16/32, cl 0fh adh 11-xxx-xxx vector shrd mem16/32, reg16/32, cl 0fh adh mm-xxx-xxx vector sldt mreg16 0fh 00h 11-000-xxx vector sldt mem16 0fh 00h mm-000-xxx vector smsw mreg16 0fh 01h 11-100-xxx vector smsw mem16 0fh 01h mm-100-xxx vector table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
80 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information stc f9h vector std fdh vector sti fbh vector stosb mem8, al aah long store, alux stosw mem16, ax abh long store, alux stosd mem32, eax abh long store, alux str mreg16 0fh 00h 11-001-xxx vector str mem16 0fh 00h mm-001-xxx vector sub mreg8, reg8 28h 11-xxx-xxx short alux sub mem8, reg8 28h mm-xxx-xxx long load, alux, store sub mreg16/32, reg16/32 29h 11-xxx-xxx short alu sub mem16/32, reg16/32 29h mm-xxx-xxx long load, alu, store sub reg8, mreg8 2ah 11-xxx-xxx short alux sub reg8, mem8 2ah mm-xxx-xxx short load, alux sub reg16/32, mreg16/32 2bh 11-xxx-xxx short alu sub reg16/32, mem16/32 2bh mm-xxx-xxx short load, alu sub al, imm8 2ch short alux sub eax, imm16/32 2dh short alu sub mreg8, imm8 80h 11-101-xxx short alux sub mem8, imm8 80h mm-101-xxx long load, alux, store sub mreg16/32, imm16/32 81h 11-101-xxx short alu sub mem16/32, imm16/32 81h mm-101-xxx long load, alu, store sub mreg16/32, imm8 (signed ext.) 83h 11-101-xxx short alux sub mem16/32, imm8 (signed ext.) 83h mm-101-xxx long load, alux, store syscall 0fh 05h vector sysret 0fh 07h vector test mreg8, reg8 84h 11-xxx-xxx short alux test mem8, reg8 84h mm-xxx-xxx vector test mreg16/32, reg16/32 85h 11-xxx-xxx short alu test mem16/32, reg16/32 85h mm-xxx-xxx vector test al, imm8 a8h long alux test eax, imm16/32 a9h long alu test mreg8, imm8 f6h 11-000-xxx long alux test mem8, imm8 f6h mm-000-xxx long load, alux test mreg16/32, imm16/32 f7h 11-000-xxx long alu table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 81 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information test mem16/32, imm16/32 f7h mm-000-xxx long load, alu verr mreg16 0fh 00h 11-100-xxx vector verr mem16 0fh 00h mm-100-xxx vector verw mreg16 0fh 00h 11-101-xxx vector verw mem16 0fh 00h mm-101-xxx vector wait 9bh vector wbinvd 0fh 09h vector wrmsr 0fh 30h vector xadd mreg8, reg8 0fh c0h 11-100-xxx vector xadd mem8, reg8 0fh c0h mm-100-xxx vector xadd mreg16/32, reg16/32 0fh c1h 11-101-xxx vector xadd mem16/32, reg16/32 0fh c1h mm-101-xxx vector xchg reg8, mreg8 86h 11-xxx-xxx vector xchg reg8, mem8 86h mm-xxx-xxx vector xchg reg16/32, mreg16/32 87h 11-xxx-xxx vector xchg reg16/32, mem16/32 87h mm-xxx-xxx vector xchg eax, eax 90h short limm xchg eax, ecx 91h long alu, alu, alu xchg eax, edx 92h long alu, alu, alu xchg eax, ebx 93h long alu, alu, alu xchg eax, esp 94h long alu, alu, alu xchg eax, ebp 95h long alu, alu, alu xchg eax, esi 96h long alu, alu, alu xchg eax, edi 97h long alu, alu, alu xlat d7h vector xor mreg8, reg8 30h 11-xxx-xxx short alux xor mem8, reg8 30h mm-xxx-xxx long load, alux, store xor mreg16/32, reg16/32 31h 11-xxx-xxx short alu xor mem16/32, reg16/32 31h mm-xxx-xxx long load, alu, store xor reg8, mreg8 32h 11-xxx-xxx short alux xor reg8, mem8 32h mm-xxx-xxx short load, alux xor reg16/32, mreg16/32 33h 11-xxx-xxx short alu xor reg16/32, mem16/32 33h mm-xxx-xxx short load, alu xor al, imm8 34h short alux xor eax, imm16/32 35h short alu table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
82 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information xor mreg8, imm8 80h 11-110-xxx short alux xor mem8, imm8 80h mm-110-xxx long load, alux, store xor mreg16/32, imm16/32 81h 11-110-xxx short alu xor mem16/32, imm16/32 81h mm-110-xxx long load, alu, store xor mreg16/32, imm8 (signed ext.) 83h 11-110-xxx short alux xor mem16/32, imm8 (signed ext.) 83h mm-110-xxx long load, alux, store table 13. floating-point instructions instruction mnemonic first byte second byte modr/m byte decode type risc86 operations f2xm1 d9h f0h short float fabs d9h f1h short float fadd st(0), st(i) 1 d8h 11-000-xxx short float fadd st(0), mem32real d8h mm-000-xxx short fload, float fadd st(i), st(0) 1 dch 11-000-xxx short float fadd st(0), mem64real dch mm-000-xxx short fload, float faddp st(i), st(0) 1 deh 11-000-xxx short float fbld dfh mm-100-xxx vector fbstp dfh mm-110-xxx vector fchs d9h e0h short float fclex dbh e2h vector fcom st(0), st(i) 1 d8h 11-010-xxx short float fcom st(0), mem32real d8h mm-010-xxx short fload, float fcom st(0), mem64real dch mm-010-xxx short fload, float fcomp st(0), st(i) 1 d8h 11-011-xxx short float fcomp st(0), mem32real d8h mm-011-xxx short fload, float fcomp st(0), mem64real dch mm-011-xxx short fload, float fcompp deh d9h 11-011-001 short float fcos d9h ffh short float fdecstp d9h f6h short float fdiv st(0), st(i) (single precision) 1 d8h 11-110-xxx short float fdiv st(0), st(i) (double precision) 1 d8h 11-110-xxx short float fdiv st(0), st(i) (extended precision) 1 d8h 11-110-xxx short float table 12. integer instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 83 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information fdiv st(i), st(0) (single precision) 1 dch 11-111-xxx short float fdiv st(i), st(0) (double precision) 1 dch 11-111-xxx short float fdiv st(i), st(0) (extended precision) 1 dch 11-111-xxx short float fdiv st(0), mem32real d8h mm-110-xxx short fload, float fdiv st(0), mem64real dch mm-110-xxx short fload, float fdivp st(0), st(i) 1 deh 11-111-xxx short float fdivr st(0), st(i) 1 d8h 11-110-xxx short float fdivr st(i), st(0) 1 dch 11-111-xxx short float fdivr st(0), mem32real d8h mm-111-xxx short fload, float fdivr st(0), mem64real dch mm-111-xxx short fload, float fdivrp st(i), st(0) 1 deh 11-110-xxx short float ffree st(i) 1 ddh 11-000-xxx short float fiadd st(0), mem32int dah mm-000-xxx short fload, float fiadd st(0), mem16int deh mm-000-xxx short fload, float ficom st(0), mem32int dah mm-010-xxx short fload, float ficom st(0), mem16int deh mm-010-xxx short fload, float ficomp st(0), mem32int dah mm-011-xxx short fload, float ficomp st(0), mem16int deh mm-011-xxx short fload, float fidiv st(0), mem32int dah mm-110-xxx short fload, float fidiv st(0), mem16int deh mm-110-xxx short fload, float fidivr st(0), mem32int dah mm-111-xxx short fload, float fidivr st(0), mem16int deh mm-111-xxx short fload, float fild mem16int dfh mm-000-xxx short fload, float fild mem32int dbh mm-000-xxx short fload, float fild mem64int dfh mm-101-xxx short fload, float fimul st(0), mem32int dah mm-001-xxx short fload, float fimul st(0), mem16int deh mm-001-xxx short fload, float fincstp d9h f7h short finit dbh e3h vector fist mem16int dfh mm-010-xxx short fload, float fist mem32int dbh mm-010-xxx short fload, float fistp mem16int dfh mm-011-xxx short fload, float fistp mem32int dbh mm-011-xxx short fload, float fistp mem64int dfh mm-111-xxx short fload, float table 13. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
84 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information fisub st(0), mem32int dah mm-100-xxx short fload, float fisub st(0), mem16int deh mm-100-xxx short fload, float fisubr st(0), mem32int dah mm-101-xxx short fload, float fisubr st(0), mem16int deh mm-101-xxx short fload, float fld st(i) 1 d9h 11-000-xxx short fload, float fld mem32real d9h mm-000-xxx short fload, float fld mem64real ddh mm-000-xxx short fload, float fld mem80real dbh mm-101-xxx vector fld1 d9h e8h short fload, float fldcw d9h mm-101-xxx vector fldenv d9h mm-100-xxx short fload, float fldl2e d9h eah short float fldl2t d9h e9h short float fldlg2 d9h ech short float fldln2 d9h edh short float fldpi d9h ebh short float fldz d9h eeh short float fmul st(0), st(i) 1 d8h 11-001-xxx short float fmul st(i), st(0) 1 dch 11-001-xxx short float fmul st(0), mem32real d8h mm-001-xxx short fload, float fmul st(0), mem64real dch mm-001-xxx short fload, float fmulp st(0), st(i) 1 deh 11-001-xxx short float fnop d9h d0h short float fpatan d9h f3h short float fprem d9h f8h short float fprem1 d9h f5h short float fptan d9h f2h vector frndint d9h fch short float frstor ddh mm-100-xxx vector fsave ddh mm-110-xxx vector fscale d9h fdh short float fsin d9h feh short float fsincos d9h fbh vector fsqrt (single precision) d9h fah short float fsqrt (double precision) d9h fah short float table 13. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
chapter 3 software environment 85 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information fsqrt (extended precision) d9h fah short float fst mem32real d9h mm-010-xxx short fstore fst mem64real ddh mm-010-xxx short fstore fst st(i) 1 ddh 11-010-xxx short fstore fstcw d9h mm-111-xxx vector fstenv d9h mm-110-xxx vector fstp mem32real d9h mm-011-xxx short fstore fstp mem64real ddh mm-011-xxx short fstore fstp mem80real d9h mm-111-xxx vector fstp st(i) 1 ddh 11-011-xxx short float fstsw ax dfh e0h vector fstsw mem16 ddh mm-111-xxx vector fsub st(0), mem32real d8h mm-100-xxx short fload, float fsub st(0), mem64real dch mm-100-xxx short fload, float fsub st(0), st(i) 1 d8h 11-100-xxx short float fsub st(i), st(0) 1 dch 11-101-xxx short float fsubp st(0), st(i) 1 deh 11-101-xxx short float fsubr st(0), mem32real d8h mm-101-xxx short fload, float fsubr st(0), mem64real dch mm-101-xxx short fload, float fsubr st(0), st(i) 1 d8h 11-100-xxx short float fsubr st(i), st(0) 1 dch 11-101-xxx short float fsubrp st(i), st(0) 1 deh 11-100-xxx short float ftst d9h e4h short float fucom ddh 11-100-xxx short float f ucomp ddh 11-101-xxx short float fucompp dah e9h short float fxam d9h e5h short float fxch d9h 11-001-xxx short float fxtract d9h f4h vector fyl2x d9h f1h short float fyl2xp1 d9h f9h short float fwait 9bh vector notes: 1. the last three bits of the modr/m byte select the stack entry st(i). table 13. floating-point instructions (continued) instruction mnemonic first byte second byte modr/m byte decode type risc86 operations
86 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 14. mmx? instructions instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations emms 0fh 77h vector movd mmreg, mreg32 1 0fh 6eh 11-xxx-xxx short meu movd mmreg, mem32 0fh 6eh mm-xxx-xxx short mload movd mreg32, mmreg 1 0fh 7eh 11-xxx-xxx short mstore, load movd mem32, mmreg 0fh 7eh mm-xxx-xxx short mstore movq mmreg1, mmreg2 0fh 6fh 11-xxx-xxx short meu movq mmreg, mem64 0fh 6fh mm-xxx-xxx short mload movq mmreg2, mmreg1 0fh 7fh 11-xxx-xxx short meu movq mem64, mmreg 0fh 7fh mm-xxx-xxx short mstore packssdw mmreg1, mmreg2 0fh 6bh 11-xxx-xxx short meu packssdw mmreg, mem64 0fh 6bh mm-xxx-xxx short mload, meu packsswb mmreg1, mmreg2 0fh 63h 11-xxx-xxx short meu packsswb mmreg, mem64 0fh 63h mm-xxx-xxx short mload, meu packuswb mmreg1, mmreg2 0fh 67h 11-xxx-xxx short meu packuswb mmreg, mem64 0fh 67h mm-xxx-xxx short mload, meu paddb mmreg1, mmreg2 0fh fch 11-xxx-xxx short meu paddb mmreg, mem64 0fh fch mm-xxx-xxx short mload, meu paddd mmreg1, mmreg2 0fh feh 11-xxx-xxx short meu paddd mmreg, mem64 0fh feh mm-xxx-xxx short mload, meu paddsb mmreg1, mmreg2 0fh ech 11-xxx-xxx short meu paddsb mmreg, mem64 0fh ech mm-xxx-xxx short mload, meu paddsw mmreg1, mmreg2 0fh edh 11-xxx-xxx short meu paddsw mmreg, mem64 0fh edh mm-xxx-xxx short mload, meu paddusb mmreg1, mmreg2 0fh dch 11-xxx-xxx short meu paddusb mmreg, mem64 0fh dch mm-xxx-xxx short mload, meu paddusw mmreg1, mmreg2 0fh ddh 11-xxx-xxx short meu paddusw mmreg, mem64 0fh ddh mm-xxx-xxx short mload, meu paddw mmreg1, mmreg2 0fh fdh 11-xxx-xxx short meu paddw mmreg, mem64 0fh fdh mm-xxx-xxx short mload, meu pand mmreg1, mmreg2 0fh dbh 11-xxx-xxx short meu pand mmreg, mem64 0fh dbh mm-xxx-xxx short mload, meu pandn mmreg1, mmreg2 0fh dfh 11-xxx-xxx short meu pandn mmreg, mem64 0fh dfh mm-xxx-xxx short mload, meu pcmpeqb mmreg1, mmreg2 0fh 74h 11-xxx-xxx short meu
chapter 3 software environment 87 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information pcmpeqb mmreg, mem64 0fh 74h mm-xxx-xxx short mload, meu pcmpeqd mmreg1, mmreg2 0fh 76h 11-xxx-xxx short meu pcmpeqd mmreg, mem64 0fh 76h mm-xxx-xxx short mload, meu pcmpeqw mmreg1, mmreg2 0fh 75h 11-xxx-xxx short meu pcmpeqw mmreg, mem64 0fh 75h mm-xxx-xxx short mload, meu pcmpgtb mmreg1, mmreg2 0fh 64h 11-xxx-xxx short meu pcmpgtb mmreg, mem64 0fh 64h mm-xxx-xxx short mload, meu pcmpgtd mmreg1, mmreg2 0fh 66h 11-xxx-xxx short meu pcmpgtd mmreg, mem64 0fh 66h mm-xxx-xxx short mload, meu pcmpgtw mmreg1, mmreg2 0fh 65h 11-xxx-xxx short meu pcmpgtw mmreg, mem64 0fh 65h mm-xxx-xxx short mload, meu pmaddwd mmreg1, mmreg2 0fh f5h 11-xxx-xxx short meu pmaddwd mmreg, mem64 0fh f5h mm-xxx-xxx short mload, meu pmulhw mmreg1, mmreg2 0fh e5h 11-xxx-xxx short meu pmulhw mmreg, mem64 0fh e5h mm-xxx-xxx short mload, meu pmullw mmreg1, mmreg2 0fh d5h 11-xxx-xxx short meu pmullw mmreg, mem64 0fh d5h mm-xxx-xxx short mload, meu por mmreg1, mmreg2 0fh ebh 11-xxx-xxx short meu por mmreg, mem64 0fh ebh mm-xxx-xxx short mload, meu pslld mmreg1, mmreg2 0fh f2h 11-xxx-xxx short meu pslld mmreg, mem64 0fh f2h mm-xxx-xxx short mload, meu pslld mmreg, imm8 0fh 72h 11-110-xxx short meu psllq mmreg1, mmreg2 0fh f3h 11-xxx-xxx short meu psllq mmreg, mem64 0fh f3h mm-xxx-xxx short mload, meu psllq mmreg, imm8 0fh 73h 11-110-xxx short meu psllw mmreg1, mmreg2 0fh f1h 11-xxx-xxx short meu psllw mmreg, mem64 0fh f1h mm-xxx-xxx short mload, meu psllw mmreg, imm8 0fh 71h 11-110-xxx short meu psrad mmreg1, mmreg2 0fh e2h 11-xxx-xxx short meu psrad mmreg, mem64 0fh e2h mm-xxx-xxx short mload, meu psrad mmreg, imm8 0fh 72h 11-100-xxx short meu psraw mmreg1, mmreg2 0fh e1h 11-xxx-xxx short meu psraw mmreg, mem64 0fh e1h mm-xxx-xxx short mload, meu psraw mmreg, imm8 0fh 71h 11-100-xxx short meu psrld mmreg1, mmreg2 0fh d2h 11-xxx-xxx short meu table 14. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations
88 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information psrld mmreg, mem64 0fh d2h mm-xxx-xxx short mload, meu psrld mmreg, imm8 0fh 72h 11-010-xxx short meu psrlq mmreg1, mmreg2 0fh d3h 11-xxx-xxx short meu psrlq mmreg, mem64 0fh d3h mm-xxx-xxx short mload, meu psrlq mmreg, imm8 0fh 73h 11-010-xxx short meu psrlw mmreg1, mmreg2 0fh d1h 11-xxx-xxx short meu psrlw mmreg, mem64 0fh d1h mm-xxx-xxx short mload, meu psrlw mmreg, imm8 0fh 71h 11-010-xxx short meu psubb mmreg1, mmreg2 0fh f8h 11-xxx-xxx short meu psubb mmreg, mem64 0fh f8h mm-xxx-xxx short mload, meu psubd mmreg1, mmreg2 0fh fah 11-xxx-xxx short meu psubd mmreg, mem64 0fh fah mm-xxx-xxx short mload, meu psubsb mmreg1, mmreg2 0fh e8h 11-xxx-xxx short meu psubsb mmreg, mem64 0fh e8h mm-xxx-xxx short mload, meu psubsw mmreg1, mmreg2 0fh e9h 11-xxx-xxx short meu psubsw mmreg, mem64 0fh e9h mm-xxx-xxx short mload, meu psubusb mmreg1, mmreg2 0fh d8h 11-xxx-xxx short meu psubusb mmreg, mem64 0fh d8h mm-xxx-xxx short mload, meu psubusw mmreg1, mmreg2 0fh d9h 11-xxx-xxx short meu psubusw mmreg, mem64 0fh d9h mm-xxx-xxx short mload, meu psubw mmreg1, mmreg2 0fh f9h 11-xxx-xxx short meu psubw mmreg, mem64 0fh f9h mm-xxx-xxx short mload, meu punpckhbw mmreg1, mmreg2 0fh 68h 11-xxx-xxx short meu punpckhbw mmreg, mem64 0fh 68h mm-xxx-xxx short mload, meu punpckhdq mmreg1, mmreg2 0fh 6ah 11-xxx-xxx short meu punpckhdq mmreg, mem64 0fh 6ah mm-xxx-xxx short mload, meu punpckhwd mmreg1, mmreg2 0fh 69h 11-xxx-xxx short meu punpckhwd mmreg, mem64 0fh 69h mm-xxx-xxx short mload, meu punpcklbw mmreg1, mmreg2 0fh 60h 11-xxx-xxx short meu punpcklbw mmreg, mem32 0fh 60h mm-xxx-xxx short mload, meu punpckldq mmreg1, mmreg2 0fh 62h 11-xxx-xxx short meu punpckldq mmreg, mem32 0fh 62h mm-xxx-xxx short mload, meu punpcklwd mmreg1, mmreg2 0fh 61h 11-xxx-xxx short meu punpcklwd mmreg, mem32 0fh 61h mm-xxx-xxx short mload, meu pxor mmreg1, mmreg2 0fh efh 11-xxx-xxx short meu table 14. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations
chapter 3 software environment 89 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information pxor mmreg, mem64 0fh efh mm-xxx-xxx short mload, meu notes: 1. bits 2, 1, and 0 of the modr/m byte select the integer register. table 15. 3dnow!? instructions instruction mnemonic prefix byte(s) opcode byte modr/m byte decode type risc86 operations femms 0fh 0eh vector pavgusb mmreg1, mmreg2 0fh, 0fh bfh 11-xxx-xxx short meu pavgusb mmreg, mem64 0fh, 0fh bfh mm-xxx-xxx short mload, meu pf2id mmreg1, mmreg2 0fh, 0fh 1dh 11-xxx-xxx short meu pf2id mmreg, mem64 0fh, 0fh 1dh mm-xxx-xxx short mload, meu pfacc mmreg1, mmreg2 0fh, 0fh aeh 11-xxx-xxx short meu pfacc mmreg, mem64 0fh, 0fh aeh mm-xxx-xxx short mload, meu pfadd mmreg1, mmreg2 0fh, 0fh 9eh 11-xxx-xxx short meu pfadd mmreg, mem64 0fh, 0fh 9eh mm-xxx-xxx short mload, meu pfcmpeq mmreg1, mmreg2 0fh, 0fh b0h 11-xxx-xxx short meu pfcmpeq mmreg, mem64 0fh, 0fh b0h mm-xxx-xxx short mload, meu pfcmpge mmreg1, mmreg2 0fh, 0fh 90h 11-xxx-xxx short meu pfcmpge mmreg, mem64 0fh, 0fh 90h mm-xxx-xxx short mload, meu pfcmpgt mmreg1, mmreg2 0fh, 0fh a0h 11-xxx-xxx short meu pfcmpgt mmreg, mem64 0fh, 0fh a0h mm-xxx-xxx short mload, meu pfmax mmreg1, mmreg2 0fh, 0fh a4h 11-xxx-xxx short meu pfmax mmreg, mem64 0fh, 0fh a4h mm-xxx-xxx short mload, meu pfmin mmreg1, mmreg2 0fh, 0fh 94h 11-xxx-xxx short meu pfmin mmreg, mem64 0fh, 0fh 94h mm-xxx-xxx short mload, meu pfmul mmreg1, mmreg2 0fh, 0fh b4h 11-xxx-xxx short meu pfmul mmreg, mem64 0fh, 0fh b4h mm-xxx-xxx short mload, meu pfrcp mmreg1, mmreg2 0fh, 0fh 96h 11-xxx-xxx short meu pfrcp mmreg, mem64 0fh, 0fh 96h mm-xxx-xxx short mload, meu pfrcpit1 mmreg1, mmreg2 0fh, 0fh a6h 11-xxx-xxx short meu pfrcpit1 mmreg, mem64 0fh, 0fh a6h mm-xxx-xxx short mload, meu pfrcpit2 mmreg1, mmreg2 0fh, 0fh b6h 11-xxx-xxx short meu pfrcpit2 mmreg, mem64 0fh, 0fh b6h mm-xxx-xxx short mload, meu pfrsqit1 mmreg1, mmreg2 0fh, 0fh a7h 11-xxx-xxx short meu table 14. mmx? instructions (continued) instruction mnemonic prefix byte(s) first byte modr/m byte decode type risc86 operations
90 software environment chapter 3 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information pfrsqit1 mmreg, mem64 0fh, 0fh a7h mm-xxx-xxx short mload, meu pfrsqrt mmreg1, mmreg2 0fh, 0fh 97h 11-xxx-xxx short meu pfrsqrt mmreg, mem64 0fh, 0fh 97h mm-xxx-xxx short mload, meu pfsub mmreg1, mmreg2 0fh, 0fh 9ah 11-xxx-xxx short meu pfsub mmreg, mem64 0fh, 0fh 9ah mm-xxx-xxx short mload, meu pfsubr mmreg1, mmreg2 0fh, 0fh aah 11-xxx-xxx short meu pfsubr mmreg, mem64 0fh, 0fh aah mm-xxx-xxx short mload, meu pi2fd mmreg1, mmreg2 0fh, 0fh 0dh 11-xxx-xxx short meu pi2fd mmreg, mem64 0fh, 0fh 0dh mm-xxx-xxx short mload, meu pmulhrw mmreg1, mmreg2 0fh, 0fh b7h 11-xxx-xxx short meu pmulhrw mmreg1, mem64 0fh, 0fh b7h mm-xxx-xxx short mload, meu prefetch mem8 1 0fh 0dh mm-000-xxx vector load prefetchw mem8 1,2 0fh 0dh mm-001-xxx vector load notes: 1. for prefetch and prefetchw, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. prefetchw will be implemented in a future k86 processor. on the amd-k6- iii e+ processor, this instruction performs in the same manner as the prefetch instruction. table 16. 3dnow!? technology dsp extensions instruction mnemonic prefix byte(s) opcode byte modr/m byte decode type risc86 operations pf2iw mmreg1, mmreg2 0fh, 0fh 1ch 11-xxx-xxx short meu pf2iw mmreg, mem64 0fh, 0fh 1ch mm-xxx-xxx short mload, meu pfnacc mmreg1, mmreg2 0fh, 0fh 8ah 11-xxx-xxx short meu pfnacc mmreg, mem64 0fh, 0fh 8ah mm-xxx-xxx short mload, meu pfpnacc mmreg1, mmreg2 0fh, 0fh 8eh 11-xxx-xxx short meu pfpnacc mmreg, mem64 0fh, 0fh 8eh mm-xxx-xxx short mload, meu pi2fw mmreg1, mmreg2 0fh, 0fh 0ch 11-xxx-xxx short meu pi2fw mmreg, mem64 0fh, 0fh 0ch mm-xxx-xxx short mload, meu pswapd mmreg1, mmreg2 0fh, 0fh bbh 11-xxx-xxx short meu pswapd mmreg, mem64 0fh, 0fh bbh mm-xxx-xxx short mload, meu table 15. 3dnow!? instructions (continued) instruction mnemonic prefix byte(s) opcode byte modr/m byte decode type risc86 operations
chapter 4 logic symbol diagram 91 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 4 logic symbol diagram notes: 1. the signals are grouped by function. the arrows show the direction of the signal, either into or out of the processor. signal s with double- headed arrows are bidirectional. signals with pound signs (#) are active low. 2. the vid[4:0] outputs are supported on low-power versions only. the vcc2det and vcc2h/l# outputs are supported on the cpga package only. a20m# a[31:3] ap ads# adsc# apchk# be[7:0]# ahold boff# breq hlda hold d/c# ewbe# lock# m/io# na# scyc w/r# cache# ken# pcd pwt wb/wt# clock bus arbitration clk bf[2:0] tck tdi tdo tms trst# brdy# brdyc# d[63:0] dp[7:0] pchk# eads# hit# hitm# inv ferr# ignne# flush# init intr nmi reset smi# smiact# stpclk# jtag test data and data parity inquire cycles floating-point error handling external interrupts, smm, reset and initialization address and address parity cycle definition and control cache control amd-k6- iii e+ processor 1 voltage detection 2 vcc2det vcc2h/l# vid[4:0]
92 logic symbol diagram chapter 4 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 5 signal descriptions 93 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5 signal descriptions this chapter includes a detailed description of each signal supported on the AMD-K6-IIIE+ processor. this chapter also provides tables listing the signals grouped by type, beginning on page 140. the logic symbol diagram on page 91 shows the signals grouped by function. connection diagrams and pins listed by high-level function are included in chapter 18, pin designations on page 323. 5.1 signal terminology the following terminology is used in this chapter: n driven the processor actively pulls the signal up to the high-voltage state or pulls the signal down to the low-voltage state. n floated the signal is not being driven by the processor (high-impedance state), which allows another device to drive this signal. n asserted for all active high signals, the term asserted means the signal is in the high-voltage state. for all active low signals, the term asserted means the signal is in the low-voltage state. see table 19 on page 140 for information on asserting signals synchronously and asynchronously. n negated for all active high signals, the term negated means the signal is in the low-voltage state. for all active low signals, the term negated means the signal is in the high-voltage state. n sampled the processor has measured the state of a signal at predefined points in time and will take the appropriate action based on the state of the signal. if a signal is not sampled by the processor, its assertion or negation has no effect on the operation of the processor.
94 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.2 a20m# (address bit 20 mask) pin attribute input summary a20m# is used to simulate the behavior of the 8086 when running in real mode. the assertion of a20m# causes the processor to force bit 20 of the physical address to 0 prior to accessing the caches or driving out a memory bus cycle. the clearing of address bit 20 maps addresses that extend above the 8086 1-mbyte limit to below 1 mbyte. sampled the processor samples a20m# as a level-sensitive input on every clock edge. the system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. the following list explains the effects of the processor sampling a20m# asserted under various conditions: n inquire cycles and writeback cycles are not affected by the state of a20m#. n the assertion of a20m# in system management mode (smm) is ignored. n when a20m# is sampled asserted in protected mode, it causes unpredictable processor operation. a20m# is only defined in real mode. n to ensure that a20m# is recognized before the first ads# occurs following the negation of reset, a20m# must be sampled asserted on the same clock edge that reset is sampled negated or on one of the two subsequent clock edges. n to ensure a20m# is recognized before the execution of an instruction, a serializing instruction must be executed between the instruction that asserts a20m# and the targeted instruction. (a serializing instruction is an instruction inserted between operations to enforce program order. it forces the processor to finish all modifications to flags, registers, and memory before the next instruction is executed.)
chapter 5 signal descriptions 95 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.3 a[31:3] (address bus) pin attribute a[31:5] bidirectional, a[4:3] output summary a[31:3] contain the physical address for the current bus cycle. the processor drives addresses on a[31:3] during memory and i/o cycles, and cycle definition information during special bus cycles. the processor samples addresses on a[31:5] during inquire cycles. driven, sampled, and floated as outputs: a[31:3] are driven valid off the same clock edge as ads# and remain in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. a[31:3] are driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor continues to drive the address bus while the bus is idle. as inputs: the processor samples a[31:5] during inquire cycles on the clock edge on which eads# is sampled asserted. even though a4 and a3 are not used during the inquire cycle, they must be driven to a valid state and must meet the same timings as a[31:5]. a[31:3] are floated off the clock edge that ahold or boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. the processor resumes driving a[31:3] off the clock edge on which the processor samples ahold or boff# negated and off the clock edge on which the processor negates hlda.
96 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.4 ads# (address strobe) pin attribute output summary the assertion of ads# indicates the beginning of a new bus cycle. the address bus and all cycle definition signals corresponding to this bus cycle are driven valid off the same clock edge as ads#. driven and floated ads# is asserted for one clock at the beginning of each bus cycle. for non-pipelined cycles, ads# can be asserted as early as the clock edge after the clock edge on which the last expected brdy# of the cycle is sampled asserted, resulting in a single idle state between cycles. for pipelined cycles if the processor is prepared to start a new cycle, ads# can be asserted as early as one clock edge after na# is sampled asserted. if ahold is sampled asserted, ads# is only driven in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. the processor floats ads# off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 5.5 adsc# (address strobe copy) pin attribute output summary adsc# has the identical function and timing as ads#. in the event ads# becomes too heavily loaded due to a large fanout in a system, adsc# can be used to split the load across two outputs, which can improve system timing.
chapter 5 signal descriptions 97 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.6 ahold (address hold) pin attribute input summary ahold can be asserted by the system to initiate one or more inquire cycles. to allow the system to drive the address bus during an inquire cycle, the processor floats a[31:3] and ap off the clock edge on which ahold is sampled asserted. the data bus and all other control and status signals remain under the control of the processor and are not floated. this allows a bus cycle that is in progress when ahold is sampled asserted to continue to completion. the processor resumes driving the address bus off the clock edge on which ahold is sampled negated. if ahold is sampled asserted, ads# is only asserted in order to perform a writeback cycle due to an inquire cycle that hits a modified cache line. sampled the processor samples ahold on every clock edge. ahold is recognized while init and reset are sampled asserted.
98 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.7 ap (address parity) pin attribute bidirectional summary ap contains the even parity bit for cache line addresses driven and sampled on a[31:5]. even parity means that the total number of 1 bits on ap and a[31:5] is even. (a4 and a3 are not used for the generation or checking of address parity because these bits are not required to address a cache line.) ap is driven by the processor during processor-initiated cycles and is sampled by the processor during inquire cycles. if ap does not reflect even parity during an inquire cycle, the processor asserts apchk# to indicate an address bus parity check. the processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. driven, sampled, and floated as an output: the processor drives ap valid off the clock edge on which ads# is asserted until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. ap is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor continues to drive ap while the bus is idle. as an input: the processor samples ap during inquire cycles on the clock edge on which eads# is sampled asserted. the processor floats ap off the clock edge that ahold or boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. the processor resumes driving ap off the clock edge on which the processor samples ahold or boff# negated and off the clock edge on which the processor negates hlda.
chapter 5 signal descriptions 99 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.8 apchk# (address parity check) pin attribute output summary if the processor detects an address parity error during an inquire cycle, apchk# is asserted for one clock. the processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. the processor is designed so that apchk# does not glitch, enabling the signal to be used as a clocking source for system logic. driven apchk# is driven valid off the clock edge after the clock edge on which the processor samples eads# asserted. it is negated off the next clock edge. apchk# is always driven except in the three-state test mode.
100 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.9 be[7:0]# (byte enables) pin attribute output summary be[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. the byte enables can be used to derive address bits a[2:0], which are not physically part of the processors address bus. the processor checks and generates valid data parity for the data bytes that are valid as defined by the byte enables. the eight byte enables correspond to the eight bytes of the data bus as follows: the processor expects data to be driven by the system logic on all eight bytes of the data bus during a burst cache-line read cycle, independent of the byte enables that are asserted. the byte enables are also used to distinguish between special bus cycles as defined in table 24 on page 142. driven and floated be[7:0]# are driven off the same clock edge as ads# and remain in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. be[7:0]# are driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. the processor floats be[7:0]# off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. unlike the address bus, be[7:0]# are not floated in response to ahold. n be7#: d[63:56] n be3#: d[31:24] n be6#: d[55:48] n be2#: d[23:16] n be5#: d[47:40] n be1#: d[15:8] n be4#: d[39:32] n be0#: d[7:0]
chapter 5 signal descriptions 101 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.10 bf[2:0] (bus frequency) pin attribute inputs, internal pullups summary bf[2:0] determine the internal operating frequency of the processor. the frequency of the clk input signal is multiplied internally by a ratio determined by the state of these signals as defined in table 17. bf[2:0] have weak internal pullups and default to the 3.5 multiplier if left unconnected. sampled bf[2:0] are sampled during the falling transition of reset. they must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of reset. table 17. processor-to-bus clock ratios state of bf[2:0] inputs processor-clock to bus-clock ratio 100b 2.0x 101b 3.0x 110b 6.0x 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x
102 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.11 boff# (backoff) pin attribute input summary if boff# is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state by floating the following signals: a[31:3], ads#, adsc#, ap, be[7:0]#, cache#, d[63:0], d/c#, dp[7:0], lock#, m/io#, pcd, pwt, scyc, and w/r#. these signals remain floated until boff# is sampled negated. this allows an alternate bus master or the system to control the bus. when boff# is sampled negated, any processor cycle that was aborted due to the assertion of boff# is restarted from the beginning of the cycle, regardless of the number of transfers that were completed. if boff# is sampled asserted on the same clock edge as brdy# of a bus cycle of any length, then boff# takes precedence over the brdy#. in this case, the cycle is aborted and restarted after boff# is sampled negated. sampled boff# is sampled on every clock edge. the processor floats its bus signals off the clock edge on which boff# is sampled asserted. these signals remain floated until the clock edge on which boff# is sampled negated. boff# is recognized while init and reset are sampled asserted.
chapter 5 signal descriptions 103 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.12 brdy# (burst ready) pin attribute input, internal pullup summary brdy# is asserted to the processor by system logic to indicate either that the data bus is being driven with valid data during a read cycle or that the data bus has been latched during a write cycle. if necessary, the system logic can insert bus cycle wait states by negating brdy# until it is ready to continue the data transfer. brdy# is also used to indicate the completion of special bus cycles. sampled brdy# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ads#. brdy# is ignored while the bus is idle. the processor samples the following inputs on the clock edge on which brdy# is sampled asserted: d[63:0], dp[7:0], and ken# during read cycles, ewbe# during write cycles (if not masked off), and wb/wt# during read and write cycles. if na# is sampled asserted prior to brdy#, then ken# and wb/wt# are sampled on the clock edge on which na# is sampled asserted. the number of times the processor expects to sample brdy# asserted depends on the type of bus cycle, as follows: n one time for a single-transfer cycle, a special bus cycle, or each of two cycles in an interrupt acknowledge sequence n four times for a burst cycle (once for each data transfer) brdy# can be held asserted for four consecutive clocks throughout the four transfers of the burst, or it can be negated to insert wait states.
104 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.13 brdyc# (burst ready copy) pin attribute input, internal pullup summary brdyc# has the identical function as brdy#. in the event brdy# becomes too heavily loaded due to a large fanout or loading in a system, brdyc# can be used to reduce this loading, which improves timing. sampled brdyc# is sampled every clock edge within a bus cycle starting with the clock edge after the clock edge that negates ads#. 5.14 breq (bus request) pin attribute output summary breq is asserted by the processor to request the bus in order to complete an internally pending bus cycle. the system logic can use breq to arbitrate among the bus participants. if the processor does not own the bus, breq is asserted until the processor gains access to the bus in order to begin the pending cycle or until the processor no longer needs to run the pending cycle. if the processor currently owns the bus, breq is asserted with ads#. the processor asserts breq for each assertion of ads# but does not necessarily assert ads# for each assertion of breq. driven breq is asserted off the same clock edge on which ads# is asserted. breq can also be asserted off any clock edge, independent of the assertion of ads#. breq can be negated one clock edge after it is asserted. the processor always drives breq except in the three-state test mode.
chapter 5 signal descriptions 105 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.15 cache# (cacheable access) pin attribute output summary for reads, cache# is asserted to indicate the cacheability of the current bus cycle. in addition, if the processor samples ken# asserted, which indicates the driven address is cacheable, the cycle is a 32-byte burst read cycle. for write cycles, cache# is asserted to indicate the current bus cycle is a modified cache-line writeback. ken# is ignored during writebacks. if cache# is not asserted, or if ken# is sampled negated during a read cycle, the cycle is not cacheable and defaults to a single-transfer cycle. driven and floated cache# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. cache# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 5.16 clk (clock) pin attribute input summary the clk signal is the bus clock for the processor and is the reference for all signal timings under normal operation (except for tdi, tdo, tms, and trst#). bf[2:0] determine the internal frequency multiplier applied to clk to obtain the processors core operating frequency. see bf[2:0] (bus frequency) on page 101 for a list of the processor-to-bus clock ratios. sampled the clk signal must be stable a minimum of 1.0 ms prior to the negation of reset to ensure the proper operation of the processor. see clk switching characteristics on page 298 for details regarding the clk specifications.
106 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.17 d/c# (data/code) pin attribute output summary the processor drives d/c# during a memory bus cycle to indicate whether it is addressing data or executable code. d/c# is also used to define other bus cycles, including interrupt acknowledge and special cycles. see table 23 and table 24 on page 142 for more details. driven and floated d/c# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. d/c# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. d/c# is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold.
chapter 5 signal descriptions 107 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.18 d[63:0] (data bus) pin attribute bidirectional summary d[63:0] represent the processors 64-bit data bus. each of the eight bytes of data that comprise this bus is qualified as valid by its corresponding byte enable. see be[7:0]# (byte enables) on page 100. driven, sampled, and floated as outputs: for single-transfer write cycles, the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted and d[63:0] remain in the same state until the clock edge on which brdy# is sampled asserted. if the cycle is a writebackin which case four 8-byte transfers occurd[63:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each brdy# assertion of the burst cycle is sampled. if the assertion of ads# represents a pipelined write cycle that follows a read cycle, the processor does not drive d[63:0] until it is certain that contention on the data bus will not occur. in this case, d[63:0] are driven the clock edge after the last expected brdy# of the previous cycle is sampled asserted. as inputs: during read cycles, the processor samples d[63:0] on the clock edge on which brdy# is sampled asserted. the processor always floats d[63:0] except when they are being driven during a write cycle as described above. in addition, d[63:0] are floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold.
108 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.19 dp[7:0] (data parity) pin attribute bidirectional summary dp[7:0] are even parity bits for each valid byte of dataas defined by be[7:0]#driven and sampled on the d[63:0] data bus. even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is an even number. dp[7:0] are driven by the processor during write cycles and sampled by the processor during read cycles. if the processor detects bad parity on any valid byte of data during a read cycle, pchk# is asserted for one clock beginning the clock edge after brdy# is sampled asserted. the processor does not take an internal exception as the result of detecting a data parity check, and system logic must respond appropriately to the assertion of this signal. the eight data parity bits correspond to the eight bytes of the data bus as follows: for systems that do not support data parity, dp[7:0] should be connected to v cc3 through pullup resistors. driven, sampled, and floated as outputs: for single-transfer write cycles, the processor drives dp[7:0] with valid parity one clock edge after the clock edge on which ads# is asserted and dp[7:0] remain in the same state until the clock edge on which brdy# is sampled asserted. if the cycle is a writeback, dp[7:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each brdy# assertion of the burst cycle is sampled. as inputs: during read cycles, the processor samples dp[7:0] on the clock edge brdy# is sampled asserted. n dp7: d[63:56] n dp3: d[31:24] n dp6: d[55:48] n dp2: d[23:16] n dp5: d[47:40] n dp1: d[15:8] n dp4: d[39:32] n dp0: d[7:0]
chapter 5 signal descriptions 109 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information the processor always floats dp[7:0] except when they are being driven during a write cycle as described above. in addition, dp[7:0] are floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in recognition of hold. 5.20 eads# (external address strobe) pin attribute input summary system logic asserts eads# during a cache inquire cycle to indicate that the address bus contains a valid address. eads# can only be driven after the system logic has taken control of the address bus by asserting ahold or boff# or by receiving hlda. the processor responds to the sampling of eads# and the address bus by driving hit#, which indicates if the inquired cache line exists in the processors caches, and hitm#, which indicates if it is in the modified state. sampled if ahold or boff# is asserted by the system logic in order to execute a cache inquire cycle, the processor begins sampling eads# two clock edges after ahold or boff# is sampled asserted. if the system logic asserts hold in order to execute a cache inquire cycle, the processor begins sampling eads# two clock edges after the clock edge hlda is asserted by the processor. eads# is ignored during the following conditions: n one clock edge after the clock edge on which eads# is sampled asserted n two clock edges after the clock edge on which ads# is asserted n when the processor is driving the address bus n when the processor asserts hitm#
110 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.21 ewbe# (external write buffer empty) pin attribute input summary the system logic can negate ewbe# to the processor to indicate that its external write buffers are full and that additional data cannot be stored at this time. this causes the processor to delay the following activities until ewbe# is sampled asserted: n the commitment of write hit cycles to cache lines in the modified state or exclusive state in the processors caches n the decode and execution of an instruction that follows a currently-executing serializing instruction n the assertion or negation of smiact# n the entering of the halt state and the stop grant state negating ewbe# does not prevent the completion of any type of cycle that is currently in progress. sampled the processor samples ewbe# on each clock edge that brdy# is sampled asserted during all memory write cycles (except writeback cycles), i/o write cycles, and special bus cycles. if ewbe# is sampled negated, it is sampled on every clock edge until it is asserted, and then it is ignored until brdy# is sampled asserted in the next write cycle or special cycle. if efer[3] is set to 1, then ewbe# is ignored by the processor. for more information on the efer settings and ewbe#, see ewbe# control on page 229.
chapter 5 signal descriptions 111 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.22 ferr# (floating-point error) pin attribute output summary the assertion of ferr# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. this signal is provided to allow the system logic to handle this exception in a manner consistent with ibm- compatible pc/at systems. see handling floating-point exceptions on page 237 for a system logic implementation that supports floating-point exceptions. the state of the numeric error (ne) bit in cr0 does not affect the ferr# signal. the processor is designed so that ferr# does not glitch, enabling the signal to be used as a clocking source for system logic. driven the processor asserts ferr# on the instruction boundary of the next floating-point instruction, mmx instruction, 3dnow! instruction, or wait instruction that occurs following the floating-point instruction that caused the unmasked floating-point exceptionthat is, ferr# is not asserted at the time the exception occurs. the ignne# signal does not affect the assertion of ferr#. ferr# is negated during the following conditions: n following the successful execution of the floating-point instructions fclex, finit, fsave, and fstenv n under certain circumstances, following the successful execution of the floating-point instructions fldcw, fldenv, and frstor, which load the floating-point status word or the floating-point control word n following the falling transition of reset ferr# is always driven except in the three-state test mode. see ignne# (ignore numeric exception) on page 116 for more details on floating-point exceptions.
112 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.23 flush# (cache flush) pin attribute input summary in response to sampling flush# asserted, the processor writes back any cache lines in the l1 data cache or l2 cache that are in the modified state, invalidates all lines in the l1 and l2 caches, and then executes a flush acknowledge special cycle. see table 24 on page 142 for the bus definition of special cycles. in addition, flush# is sampled when reset is negated to determine if the processor enters the three-state test mode. if flush# is 0 during the falling transition of reset, the processor enters the three-state test mode instead of performing the normal reset functions. sampled flush# is sampled and latched as a falling edge-sensitive signal. during normal operation (not reset), flush# is sampled on every clock edge but is not recognized until the next instruction boundary. n if flush# is asserted synchronously (see table 19 on page 140), it can be asserted for a minimum of one clock. n if flush# is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. flush# is also sampled during the falling transition of reset. if reset and flush# are driven synchronously, flush# is sampled on the clock edge prior to the clock edge on which reset is sampled negated. if reset is driven asynchronously, the minimum setup and hold time for flush#, relative to the negation of reset, is two clocks.
chapter 5 signal descriptions 113 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.24 hit# (inquire cycle hit) pin attribute output summary the processor asserts hit# during an inquire cycle to indicate that the cache line is valid within the processors l1 and/or l2 caches (also known as a cache hit). the cache line can be in the modified, exclusive, or shared state. driven hit# is always drivenexcept in the three-state test mode and only changes state the clock edge after the clock edge on which eads# is sampled asserted. it is driven in the same state until the next inquire cycle. 5.25 hitm# (inquire cycle hit to modified line) pin attribute output summary the processor asserts hitm# during an inquire cycle to indicate that the cache line exists in the processors l1 data cache or l2 cache in the modified state. the processor performs a writeback cycle as a result of this cache hit. if an inquire cycle hits a cache line that is currently being written back, the processor asserts hitm# but does not execute another writeback cycle. the system logic must not expect the processor to assert ads# each time hitm# is asserted. driven hitm# is always drivenexcept in the three-state test modeand, in particular, is driven to represent the result of an inquire cycle the clock edge after the clock edge on which eads# is sampled asserted. if hitm# is negated in response to the inquire address, it remains negated until the next inquire cycle. if hitm# is asserted in response to the inquire address, it remains asserted throughout the writeback cycle and is negated one clock edge after the last brdy# of the writeback is sampled asserted.
114 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.26 hlda (hold acknowledge) pin attribute output summary when hold is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts hlda in an acknowledgment that these events have been completed. the processor does not assert hlda until the completion of a locked sequence of cycles. while hlda is asserted, another bus master can drive cycles on the bus, including inquire cycles to the processor. the following signals are floated when hlda is asserted: a[31:3], ads#, adsc#, ap, be[7:0]#, cache#, d[63:0], d/c#, dp[7:0], lock#, m/io#, pcd, pwt, scyc, and w/r#. the processor is designed so that hlda does not glitch. driven hlda is always driven except in the three-state test mode. if a processor cycle is in progress while hold is sampled asserted, hlda is asserted one clock edge after the last brdy# of the cycle is sampled asserted. if the bus is idle, hlda is asserted one clock edge after hold is sampled asserted. hlda is negated one clock edge after the clock edge on which hold is sampled negated. the assertion of hlda is independent of the sampled state of boff#. the processor floats the bus every clock in which hlda is asserted.
chapter 5 signal descriptions 115 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.27 hold (bus hold request) pin attribute input summary the system logic can assert hold to gain control of the processors bus. when hold is sampled asserted, the processor completes the current bus cycles, floats the processor bus, and asserts hlda in an acknowledgment that these events have been completed. sampled the processor samples hold on every clock edge. if a processor cycle is in progress while hold is sampled asserted, hlda is asserted one clock edge after the last brdy# of the cycle is sampled asserted. if the bus is idle, hlda is asserted one clock edge after hold is sampled asserted. hold is recognized while init and reset are sampled asserted.
116 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.28 ignne# (ignore numeric exception) pin attribute input summary ignne#, in conjunction with the numeric error (ne) bit in the cr0 register, is used by the system logic to control the effect of an unmasked floating-point exception on a previous floating-point instruction during the execution of a floating-point instruction, mmx instruction, 3dnow! instruction, or the wait instructionhereafter referred to as the target instruction. if an unmasked floating-point exception is pending and the target instruction is considered error-sensitive, then the relationship between ne and ignne# is as follows: n if ne = 0, then: ? if ignne# is sampled asserted, the processor ignores the floating-point exception and continues with the execution of the target instruction. ? if ignne# is sampled negated, the processor waits until it samples ignne#, intr, smi#, nmi, or init asserted. ? if ignne# is sampled asserted while waiting, the processor ignores the floating-point exception and continues with the execution of the target instruction. ? if intr, smi#, nmi, or init is sampled asserted while waiting, the processor handles its assertion appropriately. n if ne = 1, the processor invokes the int 10h exception handler. if an unmasked floating-point exception is pending and the target instruction is considered error-insensitive, then the processor ignores the floating-point exception and continues with the execution of the target instruction. ferr# is not affected by the state of the ne bit or ignne#. ferr# is always asserted at the instruction boundary of the target instruction that follows the floating-point instruction that caused the unmasked floating-point exception.
chapter 5 signal descriptions 117 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information this signal is provided to allow the system logic to handle exceptions in a manner consistent with ibm-compatible pc/at systems. sampled the processor samples ignne# as a level-sensitive input on every clock edge. the system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. 5.29 init (initialization) pin attribute input summary the assertion of init causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx state, model-specific registers, the cd and nw bits of the cr0 register, and other specific internal resources. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. sampled init is sampled and latched as a rising edge-sensitive signal. init is sampled on every clock edge but is not recognized until the next instruction boundary. during an i/o write cycle, it must be sampled asserted a minimum of three clock edges before brdy# is sampled asserted if it is to be recognized on the boundary between the i/o write instruction and the following instruction. n if init is asserted synchronously (see table 19 on page 140), it can be asserted for a minimum of one clock. n if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
118 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.30 intr (maskable interrupt) pin attribute input summary intr is the systems maskable interrupt input to the processor. when the processor samples and recognizes intr asserted, the processor executes a pair of interrupt acknowledge bus cycles and then jumps to the interrupt service routine specified by the interrupt number that was returned during the interrupt acknowledge sequence. the processor only recognizes intr if the interrupt flag (if) in the eflags register equals 1. sampled the processor samples intr as a level-sensitive input on every clock edge, but the interrupt request is not recognized until the next instruction boundary. the system logic can drive intr either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. in order to be recognized, intr must remain asserted until an interrupt acknowledge sequence is complete. 5.31 inv (invalidation request) pin attribute input summary during an inquire cycle, the state of inv determines whether an addressed cache line that is found in the processors l1 and/or l2 caches transitions to the invalid state or the shared state. if inv is sampled asserted during an inquire cycle, the processor transitions the cache line (if found) to the invalid state, regardless of its previous state. if inv is sampled negated during an inquire cycle, the processor transitions the cache line (if found) to the shared state. in either case, if the cache line is found in the modified state, the processor writes it back to memory before changing its state. sampled inv is sampled on the clock edge on which eads# is sampled asserted.
chapter 5 signal descriptions 119 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.32 ken# (cache enable) pin attribute input summary if ken# is sampled asserted, it indicates that the address presented by the processor is cacheable. if ken# is sampled asserted and the processor intends to perform a cache-line fill (signified by the assertion of cache#), the processor executes a 32-byte burst read cycle and expects to sample brdy# asserted a total of four times. if ken# is sampled negated during a read cycle, a single-transfer cycle is executed and the processor does not cache the data. for write cycles, cache# is asserted to indicate the current bus cycle is a modified cache-line writeback. ken# is ignored during writebacks. if pcd is asserted during a bus cycle, the processor does not cache any data read during that cycle, regardless of the state of ken# . see pcd (page cache disable) on page 124 for more details. if the processor has sampled the state of ken# during a cycle, and that cycle is aborted due to the sampling of boff# asserted, the system logic must ensure that ken# is sampled in the same state when the processor restarts the aborted cycle. sampled ken# is sampled on the clock edge on which the first brdy# or na# of a read cycle is sampled asserted. if the read cycle is a burst, ken# is ignored during the last three assertions of brdy#. ken# is sampled during read cycles only when cache# is asserted.
120 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.33 lock# (bus lock) pin attribute output summary the processor asserts lock# during a sequence of bus cycles to ensure that the cycles are completed without allowing other bus masters to intervene. locked operations consist of two to five bus cycles. lock# is asserted during the following operations: n an interrupt acknowledge sequence n descriptor table accesses n page directory and page table accesses n xchg instruction n an instruction with an allowable lock prefix in order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processors caches are flushed and invalidated from the caches prior to the locked operation. if the cache line is in the modified state, it is written back and invalidated prior to the locked operation. likewise, any data read during a locked operation is not cached. the processor is designed so that lock# does not glitch. driven and floated during a locked cycle, lock# is asserted off the same clock edge on which ads# is asserted and remains asserted until the last brdy# of the last bus cycle is sampled asserted. the processor negates lock# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. lock# is floated off the clock edge on which boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold. when lock# is floated due to boff# sampled asserted, the system logic is responsible for preserving the lock condition while lock# is in the high-impedance state.
chapter 5 signal descriptions 121 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.34 m/io# (memory or i/o) pin attribute output summary the processor drives m/io# during a bus cycle to indicate whether it is addressing the memory or i/o space. if m/io# = 1, the processor is addressing memory or a memory-mapped i/o port as the result of an instruction fetch or an instruction that loads or stores data. if m/io# = 0, the processor is addressing an i/o port during the execution of an i/o instruction. in addition, m/io# is used to define other bus cycles, including interrupt acknowledge and special cycles. see table 23 and table 24 on page 142 for more details. driven and floated m/io# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. m/io# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. m/io# is floated off the clock edge on which boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
122 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.35 na# (next address) pin attribute input summary system logic asserts na# to indicate to the processor that it is ready to accept another bus cycle pipelined into the previous bus cycle. ads#, along with address and status signals, can be asserted as early as one clock edge after na# is sampled asserted if the processor is prepared to start a new cycle. because the processor allows a maximum of two cycles to be in progress at a time, the assertion of na# is sampled while two cycles are in progress, but ads# is not asserted until the completion of the first cycle. sampled na# is sampled every clock edge during bus cycles, starting one clock edge after the clock edge that negates ads#, until the last expected brdy# of the last executed cycle is sampled asserted (with the exception of the clock edge after the clock edge that negates the ads# for a second pending cycle). because the processor latches na# when sampled, the system logic only needs to assert na# for one clock.
chapter 5 signal descriptions 123 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.36 nmi (non-maskable interrupt) pin attribute input summary when nmi is sampled asserted, the processor jumps to the interrupt service routine defined by interrupt number 02h. unlike the intr signal, software cannot mask the effect of nmi if it is sampled asserted by the processor. however, nmi is temporarily masked upon entering system management mode (smm). in addition, an interrupt acknowledge cycle is not executed because the interrupt number is predefined. if nmi is sampled asserted while the processor is executing the interrupt service routine for a previous nmi, the subsequent nmi remains pending until the completion of the execution of the iret instruction at the end of the interrupt service routine. sampled nmi is sampled and latched as a rising edge-sensitive signal. during normal operation, nmi is sampled on every clock edge but is not recognized until the next instruction boundary. n if nmi is asserted synchronously (see table 19 on page 140), it can be asserted for a minimum of one clock. n if nmi is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
124 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.37 pcd (page cache disable) pin attribute output summary the processor drives pcd to indicate the operating systems specification of cacheability for the page being addressed. system logic can use pcd to control external caching. if pcd is asserted, the addressed page is not cached. if pcd is negated, the cacheability of the addressed page depends upon the state of cache# and ken#. the state of pcd depends upon the processors operating mode and the state of certain bits in its control registers and tlb as follows: n in real mode, or in protected and virtual-8086 modes while paging is disabled (pg bit in cr0 set to 0): pcd output = cd bit in cr0 n in protected and virtual-8086 modes while caching is enabled (cd bit in cr0 set to 0) and paging is enabled (pg bit in cr0 set to 1): ? for accesses to i/o space, page directory entries, and other non-paged accesses: pcd output = pcd bit in cr3 ? for accesses to 4-kbyte page table entries or 4-mbyte pages: pcd output = pcd bit in page directory entry ? for accesses to 4-kbyte pages: pcd output = pcd bit in page table entry driven and floated pcd is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. pcd is floated off the clock edge that boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
chapter 5 signal descriptions 125 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.38 pchk# (parity check) pin attribute output summary the processor asserts pchk# during read cycles if it detects an even parity error on one or more valid bytes of d[63:0] during a read cycle. ( even parity means that the total number of 1 bits within each byte of data and its respective data parity bit is even.) the processor checks data parity for the data bytes that are valid, as defined by be[7:0]#, the byte enables. pchk# is always driven but is only asserted for memory and i/o read bus cycles and the second cycle of an interrupt acknowledge sequence. pchk# is not driven during any type of write cycles or special bus cycles. the processor does not take an internal exception as the result of detecting a data parity error, and system logic must respond appropriately to the assertion of this signal. the processor is designed so that pchk# does not glitch, enabling the signal to be used as a clocking source for system logic. driven pchk# is always driven except in the three-state test mode. for each brdy# returned to the processor during a read cycle with a parity error detected on the data bus, pchk# is asserted for one clock, one clock edge after brdy# is sampled asserted.
126 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.39 pwt (page writethrough) pin attribute output summary the processor drives pwt to indicate the operating systems specification of the writeback state or writethrough state for the page being addressed. pwt, together with wb/wt#, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. see wb/wt# (writeback or writethrough) on page 139 for more details. the state of pwt depends upon the processors operating mode and the state of certain bits in its control registers and tlb as follows: n in real mode, or in protected and virtual-8086 modes while paging is disabled (pg bit in cr0 set to 0): pwt output = 0 (writeback state) n in protected and virtual-8086 modes while paging is enabled (pg bit in cr0 set to 1): ? for accesses to i/o space, page directory entries, and other non-paged accesses: pwt output = pwt bit in cr3 ? for accesses to 4-kbyte page table entries or 4-mbyte pages: pwt output = pwt bit in page directory entry ? for accesses to 4-kbyte pages: pwt output = pwt bit in page table entry driven and floated pwt is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. pwt is floated off the clock edge on which boff# is sampled asserted and off the clock edge on which the processor asserts hlda in response to hold.
chapter 5 signal descriptions 127 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.40 reset (reset) pin attribute input summary when the processor samples reset asserted, it immediately flushes and initializes all internal resources and its internal state including its pipelines and caches, the floating-point state, the mmx state, the 3dnow! state, and all registers, and then the processor jumps to address ffff_fff0h to start instruction execution. the flush# signal is sampled during the falling transition of reset to invoke the three-state test mode. sampled reset is sampled as a level-sensitive input on every clock edge. system logic can drive the signal either synchronously or asynchronously. during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification before it is negated. during a warm reset, while clk and v cc are within their specification, reset must remain asserted for a minimum of 15 clocks prior to its negation.
128 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.41 rsvd (reserved) pin attribute not applicable summary reserved signals are a special class of pins that can be treated in one of the following ways: n as no-connect (nc) pins, in which case these pins are left unconnected n as pins connected to the system logic as defined by the industry-standard super7 and socket 7 interface n any combination of nc and socket 7 pins in any case, if the rsvd pins are treated accordingly, the normal operation of the AMD-K6-IIIE+ processor is not adversely affected in any manner.
chapter 5 signal descriptions 129 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.42 scyc (split cycle) pin attribute output summary the processor asserts scyc during misaligned, locked transfers on the d[63:0] data bus. the processor generates additional bus cycles to complete the transfer of misaligned data. for purposes of bus cycles, the term aligned means: n any 1-byte transfers n 2-byte and 4-byte transfers that lie within 4-byte address boundaries n 8-byte transfers that lie within 8-byte address boundaries driven and floated scyc is asserted off the same clock edge as ads#, and negated off the clock edge on which na# or the last expected brdy# of the entire locked sequence is sampled asserted. scyc is only valid during locked memory cycles. scyc is floated off the clock edge on which boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
130 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.43 smi# (system management interrupt) pin attribute input, internal pullup summary the assertion of smi# causes the processor to enter system management mode (smm). upon recognizing smi#, the processor performs the following actions, in the order shown: 1. flushes its instruction pipelines 2. completes all pending and in-progress bus cycles 3. acknowledges the interrupt by asserting smiact# after sampling ewbe# asserted (if ewbe# is masked off, then smiact# is not affected by ewbe#) 4. saves the internal processor state in smm memory 5. disables interrupts by clearing the interrupt flag (if) in eflags and disables nmi interrupts 6. jumps to the entry point of the smm service routine at the smm base physical address, which defaults to 0003_8000h in smm memory see system management mode (smm) on page 241 for more details regarding smm. sampled smi# is sampled and latched as a falling edge-sensitive signal. smi# is sampled on every clock edge but is not recognized until the next instruction boundary. if smi# is to be recognized on the instruction boundary associated with a brdy#, it must be sampled asserted a minimum of three clock edges before the brdy# is sampled asserted. n if smi# is asserted synchronously (see table 19 on page 140), it can be asserted for a minimum of one clock. n if smi# is asserted asynchronously, it must have been negated for a minimum of two clocks followed by an assertion of a minimum of two clocks. a second assertion of smi# while in smm is latched but is not recognized until the smm service routine is exited.
chapter 5 signal descriptions 131 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.44 smiact# (system management interrupt active) pin attribute output summary the processor acknowledges the assertion of smi# with the assertion of smiact# to indicate that the processor has entered system management mode (smm). the system logic can use smiact# to enable smm memory. see smi# (system management interrupt) on page 130 for more details. see system management mode (smm) on page 241 for more details regarding smm. driven the processor asserts smiact# after the last brdy# of the last pending bus cycle is sampled asserted (including all pending write cycles) and after ewbe# is sampled asserted (if ewbe# is masked off, then smiact# is not affected by ewbe#). smiact# remains asserted until after the last brdy# of the last pending bus cycle associated with exiting smm is sampled asserted. smiact# remains asserted during any flush, internal snoop, or writeback cycle due to an inquire cycle.
132 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.45 stpclk# (stop clock) pin attribute input, internal pullup summary the assertion of stpclk# causes the processor to enter the stop grant state, during which the processors internal clock is stopped. from the stop grant state, the processor can subsequently transition to the stop clock state, in which the bus clock clk is stopped. upon recognizing stpclk#, the processor performs the following actions, in the order shown: 1. flushes its instruction pipelines 2. completes all pending and in-progress bus cycles 3. acknowledges the stpclk# assertion by executing a stop grant special bus cycle (see table 24 on page 142) 4. stops its internal clock after brdy# of the stop grant special bus cycle is sampled asserted and after ewbe# is sampled asserted (if ewbe# is masked off, then entry into the stop grant state is not affected by ewbe#) 5. enters the stop clock state if the system logic stops the bus clock clk (optional) see clock control on page 277 for more details regarding clock control. sampled stpclk# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. system logic can drive the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. stpclk# must remain asserted until recognized, which is indicated by the completion of the stop grant special cycle.
chapter 5 signal descriptions 133 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.46 tck (test clock) pin attribute input, internal pullup summary tck is the clock for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 253 for details regarding the operation of the tap controller. sampled the processor always samples tck, except while trst# is asserted. 5.47 tdi (test data input) pin attribute input, internal pullup summary tdi is the serial test data and instruction input for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 253 for details regarding the operation of the tap controller. sampled the processor samples tdi on every rising tck edge, but only while in the shift-ir and shift-dr states. 5.48 tdo (test data output) pin attribute output summary tdo is the serial test data and instruction output for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 253 for details regarding the operation of the tap controller. driven and floated the processor drives tdo on every falling tck edge, but only while in the shift-ir and shift-dr states. tdo is floated at all other times.
134 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.49 tms (test mode select) pin attribute input, internal pullup summary tms specifies the test function and sequence of state changes for boundary-scan testing using the test access port (tap). see boundary-scan test access port (tap) on page 253 for details regarding the operation of the tap controller. sampled the processor samples tms on every rising tck edge. if tms is sampled high for five or more consecutive clocks, the tap controller enters its test-logic-reset state, regardless of the controller state. this action is the same as that achieved by asserting trst#. 5.50 trst# (test reset) pin attribute input, internal pullup summary the assertion of trst# initializes the test access port (tap) by resetting its state machine to the test-logic-reset state. see boundary-scan test access port (tap) on page 253 for details regarding the operation of the tap controller. sampled trst# is a completely asynchronous input that does not require a minimum setup and hold time relative to tck. see table 70 on page 310 for the minimum pulse width requirement.
chapter 5 signal descriptions 135 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.51 vcc2det (vcc2 detect) pin attribute output (supported on the cpga package only) summary vcc2det is internally tied to v ss (logic level 0) to indicate to the system logic that it must supply the specified dual-voltage requirements to the v cc2 and v cc3 pins. the v cc2 pins supply voltage to the processor core, independent of the voltage supplied to the i/o buffers on the v cc3 pins. upon sampling vcc2det low, system logic should sample vcc2h/l# to identify core voltage requirements note that this pin is not supported on the obga package. driven vcc2det always equals 0 and is never floatedeven during the three-state test mode.
136 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.52 vcc2h/l# (vcc2 high/low) pin attribute output (supported on the cpga package only) summary vcc2h/l# is internally tied to v ss (logic level 0) to indicate to the system logic that it must supply the specified processor core voltage to the v cc2 pins. the v cc2 pins supply voltage to the processor core, independent of the voltage supplied to the i/o buffers on the v cc3 pins. upon sampling vcc2det low to identify dual-voltage processor requirements, system logic should sample vcc2h/l# to identify the core voltage requirements: 2.9-v and 3.2-v products (high) or 2.4-v and lower products (low). n vcc2h/l# is only driven high on older legacy (0.35-micron process technology) amd-k6 processors to indicate core voltages of 2.9 v and 3.2 v. n vcc2h/l# is driven low for all amd-k6 processors with a core voltage requirement of 2.4 v or less. note that all amd products based on the 0.18-micron process technology, including the AMD-K6-IIIE+ processor, are 2.0 v or less. note that this pin is not supported on the obga package. driven vcc2h/l# always equals 0 and is never floated for 2.4-v and lower products even during the three-state test mode. to ensure proper operation for 2.9-v and 3.2-v products, system logic that samples vcc2h/l# should design a weak pullup resistor for this signal. table 18. output pin float conditions for vcc2 high/low name floated at: vcc2det 1 notes: 1. all outputs except vcc2det, vcc2h/l#, and tdo float during the three-state test mode. always driven vcc2h/l# 1 always driven
chapter 5 signal descriptions 137 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.53 vid[4:0] (voltage identification) pin attribute output summary for amd powernow! technology-enabled processors, the vid[4:0] signals are used to drive the vid inputs of the dc/dc regulator that generates the core voltage for the processor. the processor vid[4:0] outputs default to 01010b when reset is sampled asserted. note that these pins are supported on the low-power versions only of the amd-k6-iii+ processor. for more information about these signals, see the embedded amd-k6? processors bios design guide application note , order# 23913. driven vid[4:0] are initialized to the default state after reset is sampled asserted, the cpu input clock is running, and the core and i/o voltages are applied. thereafter, the vid [4:0] outputs are always driven.
138 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.54 w/r# (write/read) pin attribute output summary the processor drives w/r# to indicate whether it is performing a write or a read cycle on the bus. in addition, w/r# is used to define other bus cycles, including interrupt acknowledge and special cycles. see table 23 and table 24 on page 142 for more details. driven and floated w/r# is driven off the same clock edge as ads# and remains in the same state until the clock edge on which na# or the last expected brdy# of the cycle is sampled asserted. w/r# is driven during memory cycles, i/o cycles, special bus cycles, and interrupt acknowledge cycles. w/r# is floated off the clock edge on which boff# is sampled asserted and off the clock edge that the processor asserts hlda in response to hold.
chapter 5 signal descriptions 139 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 5.55 wb/wt# (writeback or writethrough) pin attribute input summary wb/wt#, together with pwt, specifies the data cache-line state during cacheable read misses and write hits to shared cache lines. n if wb/wt# = 0 or pwt = 1 during a cacheable read miss or write hit to a shared cache line, the accessed line is cached in the shared state. this is referred to as the writethrough state because all write cycles to this cache line are driven externally on the bus. n if wb/wt# = 1 and pwt = 0 during a cacheable read miss or a write hit to a shared cache line, the accessed line is cached in the exclusive state. subsequent write hits to the same line cause its state to transition from exclusive to modified. this is referred to as the writeback state because the l1 data cache and the l2 cache can contain modified cache lines that are subject to be written backreferred to as a writeback cycleas the result of an inquire cycle, an internal snoop, a flush operation, or the wbinvd instruction. sampled wb/wt# is sampled on the clock edge that the first brdy# or na# of a bus cycle is sampled asserted. if the cycle is a burst read, wb/wt# is ignored during the last three assertions of brdy#. wb/wt# is sampled during memory read and non-writeback write cycles and is ignored during all other types of cycles.
140 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.56 pin tables by type table 19. input pin types name type name type a20m# 1 notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. asynchronous ignne# 1 asynchronous ahold synchronous init 2 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must rema in asserted at least two clocks. asynchronous bf[2:0] 3 3. bf[2:0] are sampled during the falling transition of reset. they must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of reset. synchronous intr 1 asynchronous boff# synchronous inv synchronous brdy# synchronous ken# synchronous brdyc# synchronous na# synchronous clk clock nmi 2 asynchronous eads# synchronous reset 4,5 4. during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach spec- ification before it is negated. 5. during a warm reset, while clk and v cc are within their specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. asynchronous ewbe# 6 6. when register bit efer[3] is set to 1, ewbe# is ignored by the processor. synchronous smi# 2 asynchronous flush# 2,7 7. flush# is also sampled during the falling transition of reset and can be asserted synchronously or asynchronously. to be samp led on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which reset is samp led negated. if asserted asynchronously, flush# must meet a minimum setup and hold time of two clocks relative to the negation of reset. asynchronous stpclk# 1 asynchronous hold synchronous wb/wt# synchronous
chapter 5 signal descriptions 141 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 20. output pin float conditions name floated at: 1 notes: 1. all outputs except vcc2det, vcc2h/l#, and tdo float during the three-state test mode. name floated at: 1 a[4:3] 2,3 2. floated off the clock edge that boff# is sampled asserted and off the clock edge that hlda is asserted. 3. floated off the clock edge that ahold is sampled asserted. hlda, ahold, boff# lock# 2 hlda, boff# ads# 2 hlda, boff# m/io# 2 hlda, boff# adsc# 2 hlda, boff# pcd 2 hlda, boff# apchk# always driven pchk# always driven be[7:0]# 2 hlda, boff# pwt 2 hlda, boff# breq always driven scyc 2 hlda, boff# cache# 2 hlda, boff# smiact# always driven d/c# 2 hlda, boff# vcc2det always driven ferr# always driven vcc2h/l# always driven hit# always driven vid[4:0] 4 4. supported on the low-power versions only. always driven hitm# always driven w/r# 2 hlda, boff# hlda always driven table 21. input/output pin float conditions name floated at: 1 notes: 1. all outputs except vcc2det and tdo float during the three-state test mode. a[31:5] 2,3 2. floated off the clock edge that boff# is sampled asserted and off the clock edge that hlda is asserted. 3. floated off the clock edge that ahold is sampled asserted. hlda, ahold, boff# ap 2,3 hlda, ahold, boff# d[63:0] 2 hlda, boff# dp[7:0] 2 hlda, boff# table 22. test pin types name type comment tck clock tdi input sampled on the rising edge of tck tdo output driven on the falling edge of tck tms input sampled on the rising edge of tck trst# input asynchronous (independent of tck)
142 signal descriptions chapter 5 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 5.57 bus cycle definitions table 23. bus cycle definition bus cycle initiated generated by the cpu generated by system logic m/io# d/c# w/r# cache# ken# code read, l1 instruction cache and l2 cache line fill 1 0 0 0 0 code read, noncacheable 1 0 0 1 x 1 notes: 1. x means dont care code read, noncacheable 1 0 0 x 1 encoding for special cycle 0 0 1 1 x interrupt acknowledge 0 0 0 1 x i/o read 0 1 0 1 x i/o write 0 1 1 1 x memory read, l1 data cache and l2 cache line fill 1 1 0 0 0 memory read, noncacheable 1 1 0 1 x memory read, noncacheable 1 1 0 x 1 memory write, l1 data cache or l2 cache writeback 1 1 1 0 x memory write, noncacheable 1 1 1 1 x table 24. special cycles special cycle a4 be7# be6# be5# be4# be3# be2# be1# be0# m/io# d/c# w/r# cache# ken# stop grant 1111110110011 x 1 notes: 1. x means dont care. enhanced power management (epm) stop grant 2 2. supported on the low-power versions only. 0101111110011x flush acknowledge (flush# sampled asserted) 0111011110011x writeback (wbinvd instruction) 0111101110011x halt 0111110110011x flush (invd, wbinvd instruction) 0111111010011x shutdown 0 1 1 1 1 1 1 1 0 0 0 1 1 x
chapter 6 amd powernow!? technology 143 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 6 amd powernow!? technology the amd powernow!? technology is an advanced second- generation power management feature that reduces the overall power consumed by the processor through control of voltage and frequency. this power saving technology is designed to be dynamic and flexible by enabling instant on-the-fly and independent control of both the processors core voltage and frequency. amd powernow! technology can be used in conjunction with the existing power management schemes in an embedded system to provide a better combination of performance and power savings than previously possible. 6.1 enhanced power management features amd powernow! technology-enabled processors include two new features specifically designed to enhance power management functionality: n dynamic core frequency control n dynamic core voltage control these enhanced power management features are accessed and controlled through an i/o block and two registers: n an aligned 16-byte block of i/o address space is defined by the enhanced power management register (epmr). n the enhanced power management register (epmr) is supported on low-power versions of the processor only. n the processor state observability register (psor) is defined differently on the low-power versions of the AMD-K6-IIIE+ processor to support amd powernow! technology features. the epmr and psor registers and the i/o block are defined in this section, followed by a discussion of how to implement and use the amd powernow! technology features (see dynamic core frequency and core voltage control on page 150). the embedded amd-k6? processors bios design guide application note , order# 23913, contains additional information.
144 amd powernow!? technology chapter 6 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information enhanced power management register (epmr) the epmr register allows software to access the aligned enhanced power management (epm) 16-byte block of i/o address space, which contains bits for enabling, controlling, and monitoring the enhanced power management features. all accesses to the epm 16-byte i/o block must be aligned dword accesses. valid accesses to the epm 16-byte block do not generate i/o cycles on the host bus, while non-aligned and non- dword accesses are passed to the host bus. the epmr is msr c000_0086h. figure 54 and table 25 define the epmr register. an assertion of reset clears all of the bits of the 16-byte i/o block to zero (excluding the voltage id output bits which default to 01010b). bios must always initialize the epmr register and enhanced power management features whenever reset is asserted. for more information about the epmr register, see the embedded amd-k6? processors bios design guide application note , order# 23913. figure 54. enhanced power management register (epmr) reserved 0 16 63 15 4 31 2 e n g s b c iobase symbol description bit iobase i/o base address 15-4 gsbc generate special bus cycle 1 en enable amd powernow! technology management 0
chapter 6 amd powernow!? technology 145 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information iobase field. the iobase field is initialized during post to an i/o address range used by an smm handler to access the enhanced power management features. because the i/o range is only enabled and accessed by the smm handler during smm, the epm features are hidden from all other software (os included)bios does not need to report the i/o range to the operating system. gsbc bit. if the gsbc bit is enabled (set to 1), a special bus cycle is generated upon a dword access within the epm 16-byte i/o block. the epm special bus cycle is defined as the processor driving d/c# = 0, m/io# = 0, and w/r# = 1, be[7:0]# = bfh and a[31:3] = 0000h. the system logic must return brdy# in response to all processor special cycles. en bit. the en bit should only be enabled (set to 1) by an smm handler when the smm handler accesses the epm features. upon exiting, the smm handler should disable the en bit and thereby protect the epm 16-byte i/o block from unwanted accesses. when the en bit is disabled, accesses to the epm block 16-byte i/o block are passed to the host bus. table 25. enhanced power management register (epmr) definition bit description r/w function 1 notes: 1. all bits default to 0 when reset is asserted. 63C16 reserved r all reserved bits are always read as 0. 15-4 i/o base address (iobase) r/w iobase defines a base address for a 16-byte block of i/o address space accessible for enabling, controlling, and monitoring the epm features. 3-2 reserved r all reserved bits are always read as 0. 1 generate special bus cycle (gsbc) r/w this bit controls whether a special bus cycle is generated upon dword accesses within the epm 16-byte i/o block. if set to 1, an epm special bus cycle is generated, where be[7:0]# = bfh and a[4:3] = 00b. 0 enable amd powernow! technology management (en) r/w this bit controls access to the i/o-mapped address space for the amd powernow! epm features. clearing this bit to zero does not affect the state of bits defined in the epm 16-byte i/o block.
146 amd powernow!? technology chapter 6 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information epm 16-byte i/o block the epm 16-byte i/o block contains one 4-byte fieldbus divisor and voltage id control (bvc)for enabling, controlling, and monitoring the enhanced power management features (see figure 55). table 26 defines the function of the bvc field within the epm 16-byte i/o block mapped by the epmr. figure 55. epm 16-byte i/o block bvc. figure 56 on page 147 shows the format, and table 27 on page 147 defines the function of each bit of the bvc field located within the epm 16-byte i/o block. table 26. epm 16-byte i/o block definition byte description r/w function 1 notes: 1. all bits default to 0 when reset is asserted. 15-12 reserved r all reserved bits are always read as 0. 11-8 bus divisor and voltage id control (bvc) r/w the bit fields within the bvc bytes allow software to change the processor bus divisor and core voltage. 7-0 reserved r all reserved bits are always read as 0. reserved 0 12 15 11 87 bvc symbol description bytes bvc bus divisor and voltage id control 11-8
chapter 6 amd powernow!? technology 147 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 56. bus divisor and voltage id control (bvc) field table 27. bus divisor and voltage id control (bvc) definition bit description r/w function 1 notes: 1. all bits default to 0 when reset is asserted, except the vido bits which default to 01010b. 31-12 stop grant time-out counter (sgtc) w writing a non-zero value to this field causes the processor to enter the epm stop grant state internally. this 20-bit value is multiplied by 4096 to determine the duration of the epm stop grant state, measured in processor bus clocks. 11 bus divisor and vid change mode (bvcm) r/w this bit controls the mode in which the bus-divisor and the voltage control bits are allowed to change. if bvcm=0, the bus divisor and voltage id changes take effect only upon entering the epm stop grant state as a result of the sgtc field being programmed. bvcm=1 is reserved. 10 voltage id control (vidc) r/w this bit controls the mode of voltage id control. if vidc=0, the proces- sor vid[4:0] pins are unchanged upon entering the epm stop grant state. if vidc=1, the processor vid[4:0] pins are programmed to the vido value upon entering the epm stop grant state. bios should ini- tialize this bit to 1 during the post routine. 9-8 bus divisor control (bdc) r/w this 2-bit field controls the mode of bus divisor control. if bdc[1:0]=00b, the bf[2:0] pins are sampled at the falling edge of reset. if bdc[1:0]=1xb, the ibf[2:0] field is sampled upon entering the epm stop grant state. bdc[1:0]=01b is reserved. bios should initialize these bits to 10b during the post routine. 7-5 internal bf divisor (ibf[2:0]) r/w if bdc[1:0]=1xb, the processor ebf[2:0] field of the psor is pro- grammed to the ibf[2:0] value upon entering the epm stop grant state. 4-0 voltage id output (vido) r/w this 5-bit value is driven out on the processor vid[4:0] pins upon entering the epm stop grant state if the vidc bit=1. these bits are ini- tialized to 01010b and driven on the processor vid[ 4:0] pins at reset. reserved 0 12 31 9 8 75 symbol description bits sgtc stop grant time-out counter 31-12 bvcm bus divisor and vid change mode 11 vidc voltage id control 10 bdc bus divisor control 9-8 ibf[2:0] internal bf divisor 7-5 vido voltage id output 4-0 v i d c ibf[2:0] 11 10 b v c m bdc vido 4 sgtc
148 amd powernow!? technology chapter 6 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information processor state observability register (psor) to support amd powernow! technology, all low-power versions of the AMD-K6-IIIE+ processor provide a different version of the processor state observability register (psor), as shown in figure 57 and fully described in this section. all standard- power versions of the processor support the psor register as defined on page 49. the psor register is msr c000_0087h. . figure 57. processor state observability register (psor )low-power versions of the processor pbf[2:0] field. this read-only field contains the bf divisor values externally applied to the processor bf[2:0] pins. these input bf values are sampled by the processor during the falling transition of reset. note: this bf divisor value may be different than the bf divisor value supplied to the processors internal pll. vid field. this read-only field contains the voltage id bits driven to the processor vid[4:0] pins at reset. these bits are initialized to 01010b and driven on the vid[4:0] pins at reset. note: low-power AMD-K6-IIIE+ processors support amd powernow! technology, which enables dynamic alteration of the processors core voltage. see enhanced power management register (epmr) on page 144 for information on programming the vid[4:0] pins. nol2 bit. this read-only bit indicates whether the processor contains an l2 cache. this bit is always set to 0 for the AMD-K6-IIIE+ processor. 2 0 63 ebf[2:0] reserved symbol description bits nol2 no l2 functionality 8 step processor stepping 7-4 ebf effective bus frequency divisor 2-0 3 4 step 7 8 9 n o l 2 vid pbf[2:0] 16 20 23 21 15 24 symbol description bits pbf pin bus frequency divisor 23-21 vid voltage id 20-16
chapter 6 amd powernow!? technology 149 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information step field. this read-only field contains the stepping id. this is identical to the value returned by cpuid standard function 1 in eax[3:0]. ebf[2:0] field. this read-only field contains the effective value of the bf divisor supplied to the processors internal pll, which allows the bios to determine the frequency of the host bus. the core frequency must first be determined using the time stamp counter (tsc) method (see time stamp counter on page 46). the core frequency is then divided by the processor-to-bus clock ratio as determined by the ebf field (see table 28). the result is the frequency of the processor bus. table 28. processor-to-bus clock ratios state of ebf[2:0] processor-to-bus clock ratio 100b 2.0x 1 notes: 1. the AMD-K6-IIIE+ processor does not support the 2.5x ratio supported by earlier amd-k6 proces- sors. instead, a ratio of 2.0x is selected when ebf[2:0] equals 100b. 101b 3.0x 110b 6.0x 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x
150 amd powernow!? technology chapter 6 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 6.2 dynamic core frequency and core voltage control amd powernow! technology-enabled processors support the ability to change the bus frequency divisor and core voltage transparently to the user during run-time. these features are implemented in conjunction with a new clock control state the epm stop grant state. for amd powernow! technology state transitions, the epmr register is accessed using an smm handler. n the smm handler initiates core voltage and frequency transitions by writing a non-zero value to the stop grant time-out counter (sgtc) field. n this action automatically places the processor into the epm stop grant state and transitions the cpu core voltage and frequency to the values specified in the voltage id output (vido) and internal bf divisor (ibf) fields of the bvc field. n once the timer of the sgtc has expired, the epm stop grant state is exited and the amd powernow! technology state transition is completed. see clock control on page 277 for more information about the epm stop grant state. effective bus frequency divisor (ebf[2:0]) the processor core frequency is controlled by the effective bus frequency divisorebf[2:0]which dictates the processor-to- bus clock ratio supplied to the processors internal pll. this processor-to-bus clock ratio is multiplied by the external bus frequency to set the frequency of operation for the processor core. n at the fall of reset, the ebf[2:0] value is determined by the state of the processor bf[2:0] input pins. n afterwards, the ebf[2:0] value can be dynamically controlled through amd powernow! technology state transitions. table 28 on page 149 lists valid ebf[2:0] states and equivalent processor-to-bus clock ratios.
chapter 6 amd powernow!? technology 151 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information dynamic core frequency control for amd powernow! technology core frequency transitions, the bvc field of the epm 16-byte i/o block is accessed through an smm handler. n to change the processor core frequency, the smm handler initiates core voltage and frequency transitions by writing a non-zero value to the sgtc field. n this action automatically places the processor into the epm stop grant state and transitions the cpu core voltage and frequency to the values specified in the vido and ibf fields of the bvc field. note: system-initiated inquire (snoop) cycles are not supported and must be prevented during the epm stop grant state. voltage identification (vid) outputs amd powernow! technology-enabled processors feature voltage id (vid) outputs to support dynamic control of the core voltage. n these outputs serve as inputs to a dc/dc regulator that supplies the processor core voltage. n based on its vid[4:0] inputs, the regulator outputs a corresponding voltage. n for those regulators that do not support vid inputs, the processor vid[4:0] outputs must be used to manipulate the regulators feedback voltage to vary the regulator output voltage.
152 amd powernow!? technology chapter 6 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 7 bus cycles 153 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 7 bus cycles the following sections describe and illustrate the timing and relationship of bus signals during various types of bus cycles. a representative set of bus cycles is illustrated. 7.1 timing diagrams the timing diagrams illustrate the signals on the external local bus as a function of time, as measured by the bus clock (clk). bus clock (clk) throughout this chapter, the term clock refers to a single bus-clock cycle. a clock extends from one rising clk edge to the next rising clk edge. the processor samples and drives most signals relative to the rising edge of clk. the exceptions to this rule include the following: n bf[2:0]sampled on the falling edge of reset n flush#sampled on the falling edge of reset, also sampled on the rising edge of clk n all inputs and outputs are sampled relative to tck in boundary-scan test mode. inputs are sampled on the rising edge of tck, outputs are driven off of the falling edge of tck. waveform definitions for each signal in the timing diagrams, the high level represents 1, the low level represents 0, and the middle level represents the floating (high-impedance) state. when both the high and low levels are shown, the meaning depends on the signal: n a single signal indicates dont care. n in the case of bus activity, if both high and low levels are shown, it indicates that the processor, alternate master, or system logic is driving a value, but this value may or may not be valid. (for example, the value on the address bus is valid only during the assertion of ads#, but addresses are also driven on the bus at other times.) figure 58 on page 154 defines the different waveform representations.
154 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information active high signals for all active high signals, the term asserted means the signal is in the high-voltage state and the term negated means the signal is in the low-voltage state. active low signals for all active low signals, the term asserted means the signal is in the low-voltage state and the term negated means the signal is in the high-voltage state. figure 58. waveform definitions waveform dont care or bus is driven description signal or bus is changing from low to high signal or bus is changing from high to low bus is changing bus is changing from valid to invalid signal or bus is floating denotes multiple clock periods
chapter 7 bus cycles 155 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 7.2 bus states the bus states illustrated in figure 59 are described in this section. figure 59. bus state machine diagram last brdy# last brdy# bus transition? no yes yes yes yes no no no no pending request? na# sampled asserted? na# sampled asserted? asserted? asserted? addr data pipe-a pipe-d idle trans bus state branch condition idle data pipeline address transition address pipeline data note: the processor transitions to the idle state on the clock edge on which boff# or reset is sampled asserted. data-na# requested data-na# last brdy# yes no asserted? pending request? no yes no yes yes na# sampled asserted? yes no
156 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information idle the processor does not drive the system bus in the idle state and remains in this state until a new bus cycle is requested. the processor enters this state off the clock edge on which the last brdy# of a cycle is sampled asserted during the following conditions: n the processor is in the data state n the processor is in the data-na# requested state and no internal pending cycle is requested in addition, the processor is forced into this state when the system logic asserts reset or boff#. the transition to this state occurs on the clock edge on which reset or boff# is sampled asserted. address in this state, the processor drives ads# to indicate the beginning of a new bus cycle by validating the address and control signals. the processor remains in this state for one clock and unconditionally enters the data state on the next clock edge. data in the data state, the processor drives the data bus during a write cycle or expects data to be returned during a read cycle. the processor remains in this state until either na# or the last brdy# is sampled asserted. if the last brdy# is sampled asserted or both the last brdy# and na# are sampled asserted on the same clock edge, the processor enters the idle state. if na# is sampled asserted first, the processor enters the data-na# requested state. data-na# requested if the processor samples na# asserted while in the data state and the current bus cycle is not completed (the last brdy# is not sampled asserted), it enters the data-na# requested state. the processor remains in this state until either the last brdy# is sampled asserted or an internal pending cycle is requested. if the last brdy# is sampled asserted before the processor drives a new bus cycle, the processor enters the idle state (no internal pending cycle is requested) or the address state (processor has a internal pending cycle). pipeline address in this state, the processor drives ads#, indicating the beginning of a new bus cycle and validating the address and control signals. in this state, the processor is still waiting for the current bus cycle to be completed (until the last brdy# is
chapter 7 bus cycles 157 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information sampled asserted). if the last brdy# is not sampled asserted, the processor enters the pipeline data state. if the processor samples the last brdy# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. a bus transition is required when the data bus direction changes between bus cycles, such as a memory write cycle followed by a memory read cycle. if a bus transition is required, the processor enters the transition state for one clock to prevent data bus contention. if a bus transition is not required, the processor enters the data state. the processor does not transition to the data-na# requested state from the pipeline address state because the processor does not begin sampling na# until it has exited the pipeline address state. pipeline data two bus cycles are executing concurrently in this state. the processor cannot issue any additional bus cycles until the current bus cycle is completed. the processor drives the data bus during write cycles or expects data to be returned during read cycles for the current bus cycle until the last brdy# of the current bus cycle is sampled asserted. if the processor samples the last brdy# asserted in this state, it determines if a bus transition is required between the current bus cycle and the pipelined bus cycle. if the bus transition is required, the processor enters the transition state for one clock to prevent data bus contention. if a bus transition is not required, the processor enters the data state (na# was not sampled asserted) or the data-na# requested state (na# was sampled asserted). transition the processor enters this state for one clock during data bus transitions and enters the data state on the next clock edge if na# is not sampled asserted. the sole purpose of this state is to avoid bus contention caused by bus transitions during pipeline operation.
158 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 7.3 memory reads and writes the AMD-K6-IIIE+ processor performs single or burst-memory bus cycles. n the single-transfer memory bus cycle transfers 1, 2, 4, or 8 bytes and requires a minimum of two clocks. n misaligned instructions or operands result in a split cycle, which requires multiple transactions on the bus. n a burst cycle consists of four back-to-back 8-byte (64-bit) transfers on the data bus. single-transfer memory read and write figure 60 on page 159 shows a single-transfer read from memory, followed by two single-transfer writes to memory. for the memory read cycle, the processor asserts ads# for one clock to validate the bus cycle and also drives a[31:3], be[7:0]#, d/c#, w/r#, and m/io# to the bus. the processor then waits for the system logic to return the data on d[63:0] (with dp[7:0] for parity checking) and assert brdy#. the processor samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads# . see brdy# (burst ready) on page 103. during the read cycle, the processor drives pcd, pwt, and cache# to indicate its caching and cache-coherency intent for the access. the system logic returns ken# and wb/wt# to either confirm or change this intent. if the processor asserts pcd and negates cache#, the accesses are noncacheable, even though the system logic asserts ken# during the brdy# to indicate its support for cacheability. the processor (which drives cache#) and the system logic (which drives ken#) must agree in order for an access to be cacheable. the processor can drive another cycle (in this example, a write cycle) by asserting ads# off the next clock edge after brdy# is sampled asserted. therefore, an idle clock is guaranteed between any two bus cycles. the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted. to minimize processor idle times, the system logic stores the address and data in write buffers, returns brdy#, and performs the store to memory later. if the processor samples ewbe# negated during a write cycle, it suspends certain activities until ewbe# is sampled asserted. see ewbe# (external write buffer empty) on page 110. in
chapter 7 bus cycles 159 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 60, the second write cycle occurs during the execution of a serializing instruction. the processor delays the following cycle until ewbe# is sampled asserted. figure 60. non-pipelined single-transfer memory read/write and write delayed by ewbe# read cycle write cycle (next cycle delayed by ewbe#) write cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# breq d[63:0] dp[7:0] cache# ewbe# ken# brdy# wb/wt# addr data idle addr addr data idle data data data idle idle idle idle idle addr
160 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information misaligned single-transfer memory read and write figure 61 on page 161 shows a misaligned (split) memory read followed by a misaligned memory write. any cycle that is not aligned as defined in scyc (split cycle) on page 129 is considered misaligned. when the processor encounters a misaligned access, it determines the appropriate pair of bus cycleseach with its own ads# and brdy# required to complete the access. the AMD-K6-IIIE+ processor performs misaligned memory reads and memory writes using least-significant bytes (lsbs) first followed by most-significant bytes (msbs). table 29 shows the order. in the first memory read cycle in figure 61, the processor reads the least-significant bytes. immediately after the processor samples brdy# asserted, it drives the second bus cycle to read the most-significant bytes to complete the misaligned transfer. similarly, the misaligned memory write cycle in figure 61 transfers the lsbs to the memory bus first. in the next cycle, after the processor samples brdy# asserted, the msbs are written to the memory bus. table 29. bus-cycle order during misaligned memory transfers type of access first cycle second cycle memory read lsbs msbs memory write lsbs msbs
chapter 7 bus cycles 161 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 61. misaligned single-transfer memory read and write lsb msb lsb msb memory read (misaligned) memory write (misaligned) clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data idle addr data data idle data addr data data idl e data
162 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information burst reads and pipelined burst reads figure 62 on page 163 shows normal burst read cycles and a pipelined burst read cycle. the AMD-K6-IIIE+ processor drives cache# and ads# together to specify that the current bus cycle is a burst cycle. if the processor samples ken# asserted with the first brdy#, it performs burst transfers. during the burst transfers, the system logic must ignore be[7:0]# and must return all eight bytes beginning at the starting address the processor asserts on a[31:3]. depending on the starting address, the system logic must determine the successive quadword addresses (a[4:3]) for each transfer in a burst, as shown in table 30. the processor expects the second, third, and fourth quadwords to occur in the sequences shown in table 30. in figure 62, the processor drives cache# throughout all burst read cycles. in the first burst read cycle, the processor drives ads# and cache#, then samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. the processor samples ken# asserted on the clock edge on which the first brdy# is sampled asserted, executes a 32-byte burst read cycle, and expects a total of four brdy# signals. an ideal no-wait state access is shown in figure 62, whereas most system logic solutions add wait states between the transfers. the second burst read cycle illustrates a similar sequence, but the processor samples na# asserted on the same clock edge that the first brdy# is sampled asserted. na# assertion indicates the system logic is requesting the processor to output the next address early (also known as a pipeline transfer request). without waiting for the current cycle to complete, the processor drives ads# and related signals for the next burst cycle. pipelining can reduce processor cycle-to-cycle idle times. table 30. a[4:3] address-generation sequence during bursts address driven by processor on a[4:3] a[4:3] addresses of subsequent quadwords 1 generated by system logic notes: 1. quadword = 8 bytes. quadword 1 quadword 2 quadword 3 quadword 4 00b 01b 10b 11b 01b 00b 11b 10b 10b 11b 00b 01b 11b 10b 01b 00b
chapter 7 bus cycles 163 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 62. burst reads and pipelined burst reads -na -addr data1 data2 data3 burst read pipelined burst read addr1 addr2 addr3 burst read clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# na# d[63:0] cache# ken# brdy# addr data idle data data data addr data data data pipe data data data data i dle
164 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information burst writeback figure 63 on page 165 shows a burst read followed by a writeback transaction. the AMD-K6-IIIE+ processor initiates writebacks under the following conditions: n replacement if a cache-line fill is initiated for a cache line currently filled with valid entries, the processor selects a line for replacement based on a least-recently-used (lru) algorithm for the l1 instruction cache and the l2 cache, and a least-recently-allocated (lra) algorithm for the l1 data cache. before a replacement is made to a l1 data cache or l2 cache line that is in the modified state, the modified line is scheduled to be written back to memory. n internal snoop the processor snoops its l1 instruction cache during read or write misses to its l1 data cache, and it snoops its l1 data cache during read misses to its l1 instruction cache. this snooping is performed to determine whether the same address is stored in both caches, a situation that is taken to imply the occurrence of self-modifying code. if an internal snoop hits a l1 data cache line in the modified state, the line is written back to memory before being invalidated. n wbinvd instruction when the processor executes a wbinvd instruction, it writes back all modified lines in the l1 data cache and l2 cache, and then invalidates all lines in all caches. n cache flush when the processor samples flush# asserted, it executes a flush acknowledge special cycle and writes back all modified lines in the l1 data cache and l2 cache, and then invalidates all lines in all caches. the processor drives writeback cycles during inquire or cache flush cycles. the writeback shown in figure 63 is caused by a cache-line replacement. the processor completes the burst read cycle that fills the cache line. immediately following the burst read cycle is the burst writeback cycle that represents the modified line to be written back to memory. d[63:0] are driven one clock edge after the clock edge on which ads# is asserted and are subsequently changed off the clock edge on which each of the four brdy# signals of the burst cycle are sampled asserted.
chapter 7 bus cycles 165 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 63. burst writeback due to cache-line replacement burst read burst writeback from l1 cache clk a[31:3] be[7:0]# ads# cache# m/io# d/c# w/r# d[63:0] ken# brdy# wb/wt# addr data idle data data data addr data idle data data data
166 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 7.4 i/o read and write basic i/o read and write the processor accesses i/o when it executes an i/o instruction (for example, in or out). figure 64 shows an i/o read followed by an i/o write. the processor drives m/io# low and d/c# high during i/o cycles. in this example, the first cycle shows a single wait state i/o read cycle. it follows the same sequence as a single-transfer memory read cycle. the processor drives ads# to initiate the bus cycle, then it samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. the system logic must return brdy# to complete the cycle. when the processor samples brdy# asserted, it can assert ads# for the next cycle off the next clock edge. (in this example, an i/o write cycle.) the i/o write cycle is similar to a memory write cycle, but the processor drives m/io# low during an i/o write cycle. the processor asserts ads# to initiate the bus cycle. the processor drives d[63:0] with valid data one clock edge after the clock edge on which ads# is asserted. the system logic must assert brdy# when the data is properly stored to the i/o destination. the processor samples brdy# on every clock edge starting with the clock edge after the clock edge that negates ads#. in this example, two wait states are inserted while the processor waits for brdy# to be asserted. figure 64. basic i/o read and write i/o read cycle i/o write cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data data idle
chapter 7 bus cycles 167 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information misaligned i/o read and write table 31 shows the misaligned i/o read and write cycle order executed by the AMD-K6-IIIE+ processor. in figure 65, the least-significant bytes (lsbs) are transferred first. immediately after the processor samples brdy# asserted, it drives the second bus cycle to transfer the most-significant bytes (msbs) to complete the misaligned bus cycle. figure 65. misaligned i/o transfer table 31. bus-cycle order during misaligned i/o transfers type of access first cycle second cycle i/o read lsbs msbs i/o write lsbs msbs lsb msb lsb msb misaligned i/o read misaligned i/o write clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] brdy# addr data data idle addr data data idle addr data data data idle addr data data data idle scyc
168 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 7.5 inquire and bus arbitration cycles the AMD-K6-IIIE+ processor provides built-in level-one (l1) data and instruction caches, and a unified level-two (l2) cache. each l1 cache is 32 kbytes and two-way set-associative. the l2 cache is 256 kbytes and four-way set-associative. the system logic or other bus master devices can initiate an inquire cycle to maintain cache/memory coherency. in response to the inquire cycle, the processor compares the inquire address with its cache tag addresses in all caches, and, if necessary, updates the mesi state of the cache line and performs writebacks to memory. an inquire cycle can be initiated by asserting ahold, boff#, or hold. ahold is exclusively used to support inquire cycles. during ahold-initiated inquire cycles, the processor only floats the address bus. boff# provides the fastest access to the bus because it aborts any processor cycle that is in-progress, whereas ahold and hold both permit an in-progress bus cycle to complete. during hold-initiated and boff#-initiated inquire cycles, the processor floats all of its bus-driving signals. the AMD-K6-IIIE+ processor does not support system-initiated inquire cycles during the enhanced power management (epm) stop grant state. for more information on the epm stop grant state, see clock control on page 277. hold and hold acknowledge cycle the system logic or another bus device can assert hold to initiate an inquire cycle or to gain full control of the bus. when the AMD-K6-IIIE+ processor samples hold asserted, it completes any in-progress bus cycle and asserts hlda to acknowledge release of the bus. the processor floats the following signals off the same clock edge on which hlda is asserted: n a[31:3] n dp[7:0] n ads# n lock# n ap# n m/io# n be[7:0]# n pcd n cache# n pwt n d[63:0] n scyc n d/c# n w/r#
chapter 7 bus cycles 169 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 66 on page 169 shows a basic hold/hlda operation. in this example, the processor samples hold asserted during the memory read cycle. it continues the current memory read cycle until brdy# is sampled asserted. the processor drives hlda and floats its outputs one clock edge after the last brdy# of the cycle is sampled asserted. the system logic can assert hold for as long as it needs to utilize the bus. the processor samples hold on every clock edge but does not assert hlda until any in-progress cycle or sequence of locked cycles is completed. when the processor samples hold negated during a hold acknowledge cycle, it negates hlda off the next clock edge. the processor regains control of the bus and can assert ads# off the same clock edge on which hlda is negated. figure 66. basic hold/hlda operation clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] hold hlda brdy#
170 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information hold-initiated inquire hit to shared or exclusive line figure 67 on page 171 shows a hold-initiated inquire cycle. in this example, the processor samples hold asserted during the burst memory read cycle. the processor completes the current cycle (until the last expected brdy# is sampled asserted), asserts hlda and floats its outputs as described in hold and hold acknowledge cycle on page 168. the system logic drives an inquire cycle within the hold acknowledge cycle. it asserts eads#, which validates the inquire address on a[31:5]. if eads# is sampled asserted before hold is sampled negated, the processor recognizes it as a valid inquire cycle. in figure 67, the processor asserts hit# and negates hitm# on the clock edge after the clock edge on which eads# is sampled asserted, indicating the current inquire cycle hit a shared or exclusive cache line. ( s hared and exclusive cache lines have not been modified and do not need to be written back.) during an inquire cycle, the processor samples inv to determine whether the addressed cache line found in the processors caches transitions to the invalid state or the shared state. in this example, the processor samples inv asserted with eads#, which invalidates the cache line. the system logic can negate hold off the same clock edge on which eads# is sampled asserted. the processor continues driving hit# in the same state until the next inquire cycle. hitm# is not asserted unless hit# is asserted.
chapter 7 bus cycles 171 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 67. hold-initiated inquire hit to shared or exclusive line burst memory read inquire clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# hold hlda eads# inv
172 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information hold-initiated inquire hit to modified line figure 68 on page 173 shows the same sequence as figure 67 on page 171, but in figure 68 the inquire cycle hits a modified line and the processor asserts both hit# and hitm#. in this example, the processor performs a writeback cycle immediately after the inquire cycle. it updates the modified cache line to external memory (normally, external cache or dram). the processor uses the address (a[31:5]) that was latched during the inquire cycle to perform the writeback cycle. the processor asserts hitm# throughout the writeback cycle and negates hitm# one clock edge after the last expected brdy# of the writeback is sampled asserted. when the processor samples eads# during the inquire cycle, it also samples inv to determine the cache line mesi state after the inquire cycle. if inv is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid state, regardless of its previous state. the cache line invalidation operation is not visible on the bus. if inv is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. in figure 68 the processor samples inv asserted during the inquire cycle. in a hold-initiated inquire cycle, the system logic can negate hold off the same clock edge on which eads# is sampled asserted. the processor drives hit# and hitm# on the clock edge after the clock edge on which eads# is sampled asserted.
chapter 7 bus cycles 17 3 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 68. hold-initiated inquire hit to modified line burst memory read inquire writeback cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# eads# hit# hitm# d[63:0] ken# brdy# hold hlda inv
174 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information ahold-initiated inquire miss ahold can be asserted by the system to initiate one or more inquire cycles. to allow the system to drive the address bus during an inquire cycle, the processor floats a[31:3] and ap off the clock edge on which ahold is sampled asserted. the data bus and all other control and status signals remain under the control of the processor and are not floated. this functionality allows a bus cycle in progress when ahold is sampled asserted to continue to completion. the processor resumes driving the address bus off the clock edge on which ahold is sampled negated. in figure 69 on page 175, the processor samples ahold asserted during the memory burst read cycle, and it floats the address bus off the same clock edge on which it samples ahold asserted. while the processor still controls the bus, it completes the current cycle until the last expected brdy# is sampled asserted. the system logic drives eads# with an inquire address on a[31:5] during an inquire cycle. the processor samples eads# asserted and compares the inquire address to its tag address in the l1 instruction and data caches, and in the l2 cache. in figure 69, the inquire address misses the tag address in the processor (both hit# and hitm# are negated). therefore, the processor proceeds to the next cycle when it samples ahold negated. (the processor can drive a new cycle by asserting ads# off the same clock edge that it samples ahold negated.) for an ahold-initiated inquire cycle to be recognized, the processor must sample ahold asserted for at least two consecutive clocks before it samples eads# asserted. if the processor detects an address parity error during an inquire cycle, apchk# is asserted for one clock. the system logic must respond appropriately to the assertion of this signal.
chapter 7 bus cycles 17 5 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 69. ahold-initiated inquire miss read inquire clk a[31:3] be[7:0]# ap apchk# ads# hit# hitm# d[63:0] ken# brdy# ahold eads# inv
176 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information ahold-initiated inquire hit to shared or exclusive line in figure 70 on page 177, the processor asserts hit# and negates hitm# off the clock edge after the clock edge on which eads# is sampled asserted, indicating the current inquire cycle hits either a shared or exclusive line. (hit# is driven in the same state until the next inquire cycle.) the processor samples inv asserted during the inquire cycle and transitions the line to the invalid state regardless of its previous state. during an ahold-initiated inquire cycle, the processor samples ahold on every clock edge until it is negated. in figure 70, the processor asserts ads# off the same clock on which ahold is sampled negated. if the inquire cycle hits a modified line, the processor performs a writeback cycle before it drives a new bus cycle. the next section describes the ahold-initiated inquire cycle that hits a modified line.
chapter 7 bus cycles 17 7 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 70. ahold-initiated inquire hit to shared or exclusive line burst memory read inquire clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# ahold inv eads#
178 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information ahold-initiated inquire hit to modified line figure 71 on page 179 shows an ahold-initiated inquire cycle that hits a modified line. during the inquire cycle in this example, the processor asserts both hit# and hitm# on the clock edge after the clock edge that it samples eads# asserted. this condition indicates that the cache line exists in the processors l1 data cache or l2 cache in the modified state. if the inquire cycle hits a modified line, the processor performs a writeback cycle immediately after the inquire cycle to update the modified cache line to shared memory (normally external cache or dram). in figure 71, the system logic holds ahold asserted throughout the inquire cycle and the processor writeback cycle. in this case, the processor is not driving the address bus during the writeback cycle because ahold is sampled asserted. the system logic writes the data to memory by using its latched copy of the inquire cycle address. if the processor samples ahold negated before it performs the writeback cycle, it drives the writeback cycle by using the address (a[31:5]) that it latched during the inquire cycle. if inv is sampled asserted during an inquire cycle, the processor transitions the line (if found) to the invalid state, regardless of its previous state (the cache invalidation operation is not visible on the bus). if inv is sampled negated during an inquire cycle, the processor transitions the line (if found) to the shared state. in either case, if the line is found in the modified state, the processor writes it back to memory before changing its state. figure 71 shows that the processor samples inv asserted during the inquire cycle and invalidates the cache line after the inquire cycle.
chapter 7 bus cycles 179 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 71. ahold-initiated inquire hit to modified line burst memory read inquire writeback clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# hit# hitm# d[63:0] ken# brdy# ahold eads# inv
180 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information ahold restriction when the system logic drives an ahold-initiated inquire cycle, it must assert ahold for at least two clocks before it asserts eads#. this requirement guarantees the processor recognizes and responds to the inquire cycle properly. the processors 32 address bus drivers turn on almost immediately after ahold is sampled negated. if the processor switches the data bus (d[63:0] and dp[7:0]) during a write cycle off the same clock edge that switches the address bus (a[31:3] and ap), the processor switches 102 drivers simultaneously, which can lead to ground-bounce spikes. therefore, before negating ahold the following restrictions must be observed by the system logic: n when the system logic negates ahold during a write cycle, it must ensure that ahold is not sampled negated on the clock edge on which brdy# is sampled asserted (see figure 72 on page 181). n when the system logic negates ahold during a writeback cycle, it must ensure that ahold is not sampled negated on the clock edge on which ads# is negated (see figure 72). n when a write cycle is pipelined into a read cycle, ahold must not be sampled negated on the clock edge after the clock edge on which the last brdy# of the read cycle is sampled asserted to avoid the processor simultaneously driving the data bus (for the pending write cycle) and the address bus off this same clock edge.
chapter 7 bus cycles 181 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 72. ahold restriction the system must ensure that ahold is not sampled negated on the clock edge that ads# is negated. legal ahold negation during write cycle illegal ahold negation during write cycle clk ads# w/r# hitm# eads# d[63:0] brdy# ahold the system must ensure that ahold is not sampled negated on the clock edge on which brdy# is sampled asserted.
182 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information bus backoff (boff#) boff# provides the fastest response among bus-hold inputs. either the system logic or another bus master can assert boff# to gain control of the bus immediately. boff# is also used to resolve potential deadlock problems that arise as a result of inquire cycles. the processor samples boff# on every clock edge. if boff# is sampled asserted, the processor unconditionally aborts any cycles in progress and transitions to a bus hold state. (see boff# (backoff) on page 102.) figure 73 on page 183 shows a read cycle that is aborted when the processor samples boff# asserted even though brdy# is sampled asserted on the same clock edge. the read cycle is restarted after boff# is sampled negated (ken# must be in the same state during the restarted cycle as its state during the aborted cycle). during a boff#-initiated inquire cycle that hits a shared or exclusive line, the processor samples boff# negated and restarts any bus cycle that was aborted when boff# was asserted. if a boff#-initiated inquire cycle hits a modified line, the processor performs a writeback cycle before it restarts the aborted cycle. if the processor samples boff# asserted on the same clock edge that it asserts ads#, ads# is floated but the system logic may erroneously interpret ads# as asserted. in this case, the system logic must properly interpret the state of ads# when boff# is negated.
chapter 7 bus cycles 183 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 73. boff# timing read backoff cycle restart read cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# boff# d[63:0] brdy#
184 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information locked cycles the processor asserts lock# during a sequence of bus cycles to ensure the cycles are completed without allowing other bus masters to intervene. locked operations can consist of two to five cycles. lock# is asserted during the following operations: n an interrupt acknowledge sequence n descriptor table accesses n page directory and page table accesses n xchg instruction n an instruction with an allowable lock prefix in order to ensure that locked operations appear on the bus and are visible to the entire system, any data operands addressed during a locked cycle that reside in the processors caches are flushed and invalidated from the caches prior to the locked operation. if the cache line is in the modified state, it is written back and invalidated prior to the locked operation. likewise, any data read during a locked operation is not cached. the processor negates lock# for at least one clock between consecutive sequences of locked operations to allow the system logic to arbitrate for the bus. the processor asserts scyc during misaligned locked transfers on the d[63:0] data bus. the processor generates additional bus cycles to complete the transfer of misaligned data. basic locked operation figure 74 on page 185 shows a pair of read-write bus cycles. it represents a typical read-modify-write locked operation. the processor asserts lock# off the same clock edge that it asserts ads# of the first bus cycle in the locked operation and holds it asserted until the last expected brdy# of the last bus cycle in the locked operation is sampled asserted. (the processor negates lock# off of the same clock edge.)
chapter 7 bus cycles 185 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 74. basic locked operation locked read cycle locked write cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# d[63:0] brdy# addr data data data idle idle addr data data data idle idle addr scyc
186 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information locked operation with boff# intervention figure 75 on page 187 shows boff# asserted within a locked read-write pair of bus cycles. in this example, the processor asserts lock# with ads# to drive a locked memory read cycle followed by a locked memory write cycle. during the locked memory write cycle in this example, the processor samples boff# asserted. the processor immediately aborts the locked memory write cycle and floats all its bus-driving signals, including lock#. the system logic or another bus master can initiate an inquire cycle or drive a new bus cycle one clock edge after the clock edge on which boff# is sampled asserted. if the system logic drives a boff#-initiated inquire cycle and hits a modified line, the processor performs a writeback cycle before it restarts the locked cycle (the processor asserts lock# during the writeback cycle). in figure 75, the processor immediately restarts the aborted locked write cycle by driving the bus off the clock edge on which boff# is sampled negated. the system logic must ensure the processor results for interrupted and uninterrupted locked cycles are consistent. that is, the system logic must guarantee the memory accessed by the processor is not modified during the time another bus master controls the bus.
chapter 7 bus cycles 187 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 75. locked operation with boff# intervention locked read cycle aborted write cycle restart write cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# boff# d[63:0] brdy#
188 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information interrupt acknowledge in response to recognizing the systems maskable interrupt (intr), the processor drives an interrupt acknowledge cycle at the next instruction boundary. during an interrupt acknowledge cycle, the processor drives a locked pair of read cycles as shown in figure 76 on page 189. the first read cycle is not functional, and the second read cycle returns the interrupt number on d[7:0] (00hCffh). table 32 shows the state of the signals during an interrupt acknowledge cycle. the system logic can drive intr either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. to ensure it is recognized, intr must remain asserted until an interrupt acknowledge sequence is complete. table 32. interrupt acknowledge operation definition processor outputs first bus cycle second bus cycle d/c# low low m/io# low low w/r# low low be[7:0]# efh feh (low byte enabled) a[31:3] 0000_0000h 0000_0000h d[63:0] (ignored) interrupt number expected from interrupt con- troller on d[7:0]
chapter 7 bus cycles 189 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 76. interrupt acknowledge operation interrupt acknowledge cycles interrupt number clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# lock# intr d[63:0] ken# brdy#
190 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 7.6 special bus cycles the AMD-K6-IIIE+ processor drives special bus cycles that include the following: n stop grant n enhanced power management n flush acknowledge n cache writeback invalidation n halt n cache invalidation n shutdown during all special cycles, d/c# = 0, m/io# = 0, and w/r# = 1. be[7:0]# and a[31:3] are driven to differentiate among the special cycles, as shown in table 33. note that the system logic must return brdy# in response to all processor special cycles. basic special bus cycle figure 77 on page 191 shows a basic special bus cycle. the processor drives d/c# = 0, m/io# = 0, and w/r# = 1 off the same clock edge that it asserts ads#. in this example, be[7:0]# = fbh and a[31:3] = 0000_0000h, which indicates that the special cycle is a halt special cycle (see table 33. encodings for special bus cycles be[7:0]# a[4:3] 1 notes: 1. a[31:5] = 0 special bus cycle cause fbh 10b stop grant stpclk# sampled asserted bfh 00b epm stop grant 2 2. supported on the low-power versions only. a dword access is made to the epm 16-byte i/o block and the gsbc bit of the epmr register is set to 1 efh 00b flush acknowledge flush# sampled asserted f7h 00b writeback wbinvd instruction fbh 00b halt hlt instruction fdh 00b flush invd,wbinvd instruction feh 00b shutdown triple fault
chapter 7 bus cycles 191 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 33). a halt special cycle is generated after the processor executes the hlt instruction. if the processor samples flush# asserted, it writes back any l1 data cache and l2 cache lines that are in the modified state and invalidates all lines in all caches. the processor then drives a flush acknowledge special cycle. if the processor executes a wbinvd instruction, it drives a writeback special cycle after the processor completes invalidating and writing back the cache lines. figure 77. basic special bus cycle (halt cycle) halt cycle a[4:3] = 00b fbh clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# brdy#
192 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information shutdown cycle in figure 78 on page 192, a shutdown (triple fault) occurs in the first half of the waveform, and a shutdown special cycle follows in the second half. the processor enters shutdown when an interrupt or exception occurs during the handling of a double fault (int 8), which amounts to a triple fault. when the processor encounters a triple fault, it stops its activity on the bus and generates the shutdown special bus cycle (be[7:0]# = feh). the system logic must assert nmi, init, reset, or smi# to get the processor out of the shutdown state. figure 78. shutdown cycle shutdown occurs (triple fault) shutdown special cycle clk a[31:3] be[7:0]# ads# lock# m/io# d/c# w/r# d[63:0] ken# brdy# a[4:3] = 00b feh
chapter 7 bus cycles 193 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information stop grant and stop clock states figure 79 on page 194 and figure 80 on page 195 show the processor transition from normal execution to the stop grant state, then to the stop clock state, back to the stop grant state, and finally back to normal execution. the series of transitions begins when the processor samples stpclk# asserted. on recognizing a stpclk# interrupt at the next instruction retirement boundary, the processor performs the following actions, in the order shown: 1. its instruction pipelines are flushed. 2. all pending and in-progress bus cycles are completed. 3. the stpclk# assertion is acknowledged by executing a stop grant special bus cycle. 4. its internal clock is stopped after brdy# of the stop grant special bus cycle is sampled asserted (if ewbe# is masked off, then entry into the stop grant state is not affected by ewbe#) and after ewbe# is sampled asserted. 5. the stop clock state is entered if the system logic stops the bus clock clk (optional). stpclk# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. the system logic drives the signal either synchronously or asynchronously. if it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. stpclk# must remain asserted until recognized, which is indicated by the completion of the stop grant special cycle.
194 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 79. stop grant and stop clock modes, part 1 stpclk# sampled asserted stop grant special cycle clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# cache# stpclk# d[63:0] ken# brdy# stop clock a[4:3] = 10b fbh
chapter 7 bus cycles 195 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 80. stop grant and stop clock modes, part 2 stop grant state (re-entered after pll stabilization) stpclk# sampled negated normal stop clock clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# cache# stpclk# d[63:0] ken# brdy#
196 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information init-initiated transition from protected mode to real mode init is typically asserted in response to a bios interrupt that writes to an i/o port. this interrupt is often in response to a ctrl-alt-del keyboard input. the bios writes to a port (similar to port 64h in the keyboard controller) that asserts init. init is also used to support 80286 software that must return to real mode after accessing extended memory in protected mode. the assertion of init causes the processor to empty its pipelines, initialize most of its internal state, and branch to address ffff_fff0h the same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx state, model-specific registers (msrs), the cd and nw bits of the cr0 register, the time stamp counter, and other specific internal resources. figure 81 on page 197 shows an example in which the operating system writes to an i/o port, causing the system logic to assert init. the sampling of init asserted starts an extended microcode sequence that terminates with a code fetch from ffff_fff0h, the reset location. init is sampled on every clock edge but is not recognized until the next instruction boundary. during an i/o write cycle, it must be sampled asserted a minimum of three clock edges before brdy# is sampled asserted if it is to be recognized on the boundary between the i/o write instruction and the following instruction. if init is asserted synchronously, it can be asserted for a minimum of one clock. if it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks.
chapter 7 bus cycles 197 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 81. init-initiated transition from protected mode to real mode code fetch ffff_fff0h init sampled asserted clk a[31:3] be[7:0]# ads# m/io# d/c# w/r# d[63:0] ken# brdy# init
198 bus cycles chapter 7 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 8 power-on configuration and initialization 199 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 8 power-on configuration and initialization on power-on the system logic must reset the AMD-K6-IIIE+ processor by asserting the reset signal. when the processor samples reset asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the mmx and 3dnow! states, and all registers. then the processor jumps to address ffff_fff0h to start instruction execution. 8.1 signals sampled during the falling transition of reset flush# flush# is sampled on the falling transition of reset to determine if the processor begins normal instruction execution or enters three-state test mode. n if flush# is high during the falling transition of reset, the processor unconditionally runs its built-in self test (bist), performs the normal reset functions, then jumps to address ffff_fff0h to start instruction execution. (see built-in self-test (bist) on page 251 for more details.) n if flush# is low during the falling transition of reset, the processor enters three-state test mode. (see three-state test mode on page 252 and flush# (cache flush) on page 112 for more details.) bf[2:0] the internal operating frequency of the processor is determined by the state of the bus frequency signals bf[2:0] when they are sampled during the falling transition of reset. the frequency of the clk input signal is multiplied internally by a ratio defined by bf[2:0]. (see bf[2:0] (bus frequency) on page 101 for the processor-clock to bus-clock ratios.)
200 power-on configuration and initialization chapter 8 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 8.2 reset requirements during the initial power-on reset of the processor, reset must remain asserted for a minimum of 1.0 ms after clk and v cc reach specification. ( see clk switching characteristics on page 298 for clock specifications. electrical data beginning on page 287 for v cc specifications.) during a warm reset while clk and v cc are within specification, reset must remain asserted for a minimum of 15 clocks prior to its negation. 8.3 state of processor after reset output signals table 34 shows the state of all processor outputs and bidirectional signals immediately after reset is sampled asserted. registers table 35 on page 201 shows the state of all architecture registers and model-specific registers (msrs) after the processor has completed its initialization due to the recognition of the assertion of reset. table 34. output signal state after reset signal state signal state a[31:3], ap floating lock# high ads#, adsc# high m/io# low apchk# high pcd low be[7:0]# floating pchk# high breq low pwt low cache# high scyc low d/c# low smiact# high d[63:0], dp[7:0] floating tdo floating ferr# high vcc2det low hit# high vcc2h/l# low hitm# high vid[4:0] 1 notes: 1. supported on low-power versions only. 01010b hlda low w/r# low
chapter 8 power-on configuration and initialization 201 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 35. register state after reset register state (hex) gdtr base:0000_0000h limit:0ffffh idtr base:0000_0000h limit:0ffffh tr 0000h ldtr 0000h eip ffff_fff0h eflags 0000_0002h eax 1 0000_0000h ebx 0000_0000h ecx 0000_0000h edx 2 0000_059xh esi 0000_0000h edi 0000_0000h ebp 0000_0000h esp 0000_0000h cs f000h ss 0000h ds 0000h es 0000h fs 0000h gs 0000h fpu stack r7Cr0 3 0000_0000_0000_0000_0000h fpu control word 3 0040h fpu status word 3 0000h fpu tag word 3 5555h fpu instruction pointer 3 0000_0000_0000h fpu data pointer 3 0000_0000_0000h fpu opcode register 3 000_0000_0000b cr0 4 6000_0010h cr2 0000_0000h cr3 0000_0000h cr4 0000_0000h dr7 0000_0400h dr6 ffff_0ff0h dr3 0000_0000h
202 power-on configuration and initialization chapter 8 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information dr2 0000_0000h dr1 0000_0000h dr0 0000_0000h mcar 3 0000_0000_0000_0000h mctr 3 0000_0000_0000_0000h tr12 3 0000_0000_0000_0000h tsc 3 0000_0000_0000_0000h efer 3 0000_0000_0000_0002h star 3 0000_0000_0000_0000h whcr 3 0000_0000_0000_0000h uwccr 3 0000_0000_0000_0000h psor 5 0000_0000_0000_01sbh pfir 3 , 5 0000_0000_0000_0000h epmr 3 , 6 0000_0000_0000_0000h notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k6- iii e+ processor signature, where x indicates the processor stepping id. 3. the contents of these registers are preserved following the recognition of init. 4. the cd and nw bits of cr0 are preserved following the recognition of init. 5. s represents the stepping. b represents psor[3:0], where psor[3] equals 0, and psor[2:0] is equal to the value of the bf[2:0] signals sampled during the falling transition of r eset. 6. supported on low-power versions only. table 35. register state after reset (continued) register state (hex)
chapter 8 power-on configuration and initialization 203 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 8.4 state of processor after init the recognition of the assertion of init causes the processor to empty its pipelines, to initialize most of its internal state, and to branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the mmx and 3dnow! states, msrs, and the cd and nw bits of the cr0 register. the edge-sensitive interrupts flush# and smi# are sampled and preserved during the init process and are handled accordingly after the initialization is complete. however, the processor resets any pending nmi interrupt upon sampling init asserted. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode.
204 power-on configuration and initialization chapter 8 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 9 cache organization 205 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 9 cache organization the following sections describe the basic architecture and resources of the AMD-K6-IIIE+ processor internal caches. the performance of the AMD-K6-IIIE+ processor is enhanced by writeback level-one (l1) and level-two (l2) caches. n the l1 cache is organized as separate 32-kbyte instruction and data caches, each with two-way set associativity. n the l2 cache is 256 kbytes, and is organized as a unified, four-way set-associative cache (see figure 82 on page 206). the cache line size is 32 bytes, and lines are fetched from external memory using an efficient pipelined burst transaction. as the l1 instruction cache is filled from the l2 cache or from external memory, each instruction byte is analyzed for instruction boundaries using predecode logic. predecoding annotates each instruction byte in the l1 instruction cache with information that later enables the decoders to efficiently decode multiple instructions simultaneously. translation lookaside buffers (tlb) are used in conjunction with the l1 cache to translate linear addresses to physical addresses. the l1 instruction cache is associated with a 64-entry tlb, while the l1 data cache is associated with a 128-entry tlb.
206 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 82. l1 and l2 cache organization for the amd-k6?- iii e+ processor the processor cache design takes advantage of a sectored organization (see figure 83). each sector consists of 64 bytes configured as two 32-byte cache lines. the two cache lines of a sector share a common tag but have separate mesi (modified, exclusive, shared, invalid) bits that track the state of each cache line. processor core system bus interface unit 128-entry tlb 64-entry tlb state bit tag ram way 0 way 1 state bit tag ram 32-kbyte l1 instruction cache 32-kbyte l1 data cache pre-decode instruction cache mesi bits tag ram way 0 way 1 mesi bits tag ram 256-kbyte l2 cache mesi bits tag ram way 0 way 1 mesi bits tag ram mesi bits tag ram way 2 way 3 mesi bits tag ram
chapter 9 cache organization 207 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information l1 instruction cache line l1 data cache line and l2 cache line note: l1 instruction-cache lines have only two coherency states (valid or invalid) rather than the four mesi coherency states of l1 data-cache and l2 cache lines. only two states are needed for the l1 instruction cache because these lines are read-only. figure 83. l1 cache sector organization 9.1 mesi states in the l1 data cache and l2 cache the state of each line in the caches is tracked by the mesi bits. the coherency of these states or mesi bits is maintained by internal processor snoops and external inquire cycles by the system logic. the following four states are defined for the l1 data cache and the l2 cache: n modified this line has been modified and is different from external memory. n exclusive in general, an exclusive line in the l1 data cache or the l2 cache is not modified and is the same as external memory. the exception is the case where a line exists in the modified state in the l1 data cache and also resides in the l2 cache. by design, the line in the l2 cache must be in the exclusive state. n shared if a cache line is in the shared state it means that the same line can exist in more than one cache system. n invalid the information in this line is not valid. tag address cache line 0 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits 1 mesi bit cache line 1 byte 31 predecode bits byte 30 predecode bits ........ ........ byte 0 predecode bits 1 mesi bit tag address cache line 0 byte 31 byte 30 ........ ........ byte 0 2 mesi bits cache line 1 byte 31 byte 30 ........ ........ byte 0 2 mesi bits
208 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 9.2 predecode bits decoding x86 instructions is particularly difficult because the instructions vary in length, ranging from 1 to 15 bytes long. predecode logic supplies the predecode bits associated with each instruction byte. predecode bits indicate the number of bytes to the start of the next x86 instruction. the predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. the predecode bits use memory separate from the 32-kbyte l1 instruction cache. the predecode bits are stored in an extended l1 instruction cache alongside each x86 instruction byte as shown in figure 83 on page 207. the l2 cache does not store predecode bits. as an instruction cache line is fetched from the l2 cache, the predecode bits are generated and stored alongside the cache line in the l1 instruction cache in the same manner as if the cache line were fetched from the processors system bus. 9.3 cache operation the operating modes for the caches are configured by software using the not writethrough (nw) and cache disable (cd) bits of control register 0 (cr0 bits 29 and 30, respectively). these bits are used in all operating modes. n when the cd and nw bits are both set to 0, the cache is fully enabled. this is the standard operating mode for the cache. if a l1 cache read miss occurs, the processor determines if the read hits the l2 cache, in which case the cache line is supplied from the l2 cache to the l1 cache. if a read misses both the l1 and the l2 caches, a line fill (32-byte burst read) on the system bus occurs in order to fetch the cache line. the cache line is then filled in both the l1 and the l2 caches. write hits to the l1 and l2 caches are updated, while write misses and writes to shared lines cause external memory updates. refer to table 39 on page 221 for a summary of cache read and write cycles and the effect of these operations on the cache mesi state. note: a write allocate operation can modify the behavior of write misses to the caches. see write allocate on page 215.
chapter 9 cache organization 209 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information the AMD-K6-IIIE+ processor does not enforce any rules of inclusion or exclusion as part of the protocol defined for the l1 and l2 caches. however, there are certain restrictions imposed by design on the allowable mesi states of a cache line that exists in both the l1 cache and the l2 cache. refer to table 40 on page 225 for a list of the valid cache-line states allowed. n when cd is set to 0 and nw is set to 1, an invalid mode of operation exists that causes a general protection fault to occur. n when cd is set to 1 (disabled) and nw is set to 0, the cache fill mechanism is disabled but the contents of the cache are still valid. the processor reads from the caches if the read hits the l1 or the l2 cache. if a read misses both the l1 and the l2 caches, a line fill does not occur on the system bus. write hits to the l1 or l2 cache are updated, while write misses and writes to shared lines cause external memory updates. if pwt is driven low and wb/wt# is sampled high, a write hit to a shared line changes the cache-line state to exclusive. n when the cd and nw bits are both set to 1, the cache is fully disabled. even though the cache is disabled, the contents are not necessarily invalid. the processor reads from the caches if the read hits the l1 or the l2 cache. if a read misses both the l1 and the l2 caches, a line fill does not occur on the system bus. if a write hits the l1 or the l2 cache, the cache is updated but an external memory update does not occur. if a cache line is in the exclusive state during a write hit, the cache-line state is changed to modified. cache lines in the shared state remain in the shared state after a write hit. write misses access external memory directly. the operating system can control the cacheability of a page. the paging mechanism is controlled by cr3, the page directory entry (pde), and the page table entry (pte). within cr3, pde, and pte are page cache disable (pcd) and page writethrough (pwt) bits. the values of the pcd and pwt bits used in table 36 on page 210 and table 37 on page 210 are taken from either the pte or pde. for more information on pcd and pwt, see pcd (page cache disable) on page 124 and pwt (page writethrough) on page 126, respectively.
210 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 36 describes how the pwt signal is driven based on the values of the pwt bits and the pg bit of cr0. table 37 describes how the pcd signal is driven based on the values of the cd bit of cr0, the pcd bits, and the pg bit of cr0. table 38 describes how the cache# signal is driven based on the cycle type, the ci bit of tr12, the pcd signal, and the uwccr model-specific register. table 36. pwt signal generation pwt bit 1 notes: 1. pwt is taken from pte or pde. pg bit of cr0 pwt signal 11high 01low 10low 00low table 37. pcd signal generation cd bit of cr0 pcd bit 1 notes: 1. pcd is taken from pte or pde. pg bit of cr0 pcd signal 1xxhigh 011high 001low 010low 000low
chapter 9 cache organization 211 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information cache-related signals complete descriptions of the signals that control cacheability and cache coherency are given on the following pages: n cache# page 105 n eads#page 109 n flush#page 112 n hit#page 113 n hitm#page 113 n invpage 118 n ken#page 119 n pcdpage 124 n pwtpage 126 n wb/wt#page 139 9.4 cache disabling and flushing l1 and l2 cache disabling to completely disable all accesses to the l1 and the l2 caches, the cd bit must be set to 1 and the caches must be completely flushed. there are three different methods for flushing the caches. the first method relies on the system logic and the other two methods rely on software. n for the system logic to flush the caches, the processor must sample flush# asserted. in this method, the processor writes back any l1 data cache and l2 cache lines that are in table 38. cache# signal generation cycle type ci bit of tr12 pcd signal access within wc/uc range 1 notes: 1. wc and uc refer to write-combining and uncacheable memory ranges as defined in the uwccr. cache# writebacks xx x low unlocked reads 00 0 low locked reads xx x high single writes xx x high any cycle except writebacks 1x x high any cycle except writebacks x1 x high any cycle except writebacks xx 1 high
212 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the modified state, invalidates all lines in all caches, and then executes a flush acknowledge special cycle (see table 24 on page 142). n the second method for flushing the caches is for software to execute the wbinvd instruction, which causes all modified lines to first be written back to memory, then marks all cache lines as invalid. alternatively, if writing modified lines back to memory is not necessary, the invd instruction can be used to invalidate all cache lines. n the third method for flushing the caches is to make use of the page flush/invalidate register (pfir), which allows cache invalidation and optional flushing of a specific 4- kbyte page from the linear address space (see page flush/invalidate register (pfir) on page 223). unlike the previous two methods of flushing the caches, this particular method requires the software to be aware of which specific pages must be flushed and invalidated. l2 cache disabling the l2 cache in the AMD-K6-IIIE+ processor can be completely disabled by setting the l2 disable (l2d) bit (efer[4]) to 1 (see extended feature enable register (efer) on page 47). if disabled in this manner, the processor does not access the l2 cache for any purpose, including allocations, read hits, write hits, snoops, inquire cycles, flushing, and read/write attempts by means of the l2aar. (see l2 cache testing on page 213.) the l1 cache operation is not affected by disabling the l2 cache. the l2d bit is provided for debug and testing purposes only. for normal operation and maximum performance, this bit must be set to 0, which is the default setting following reset. the AMD-K6-IIIE+ processor does not provide a method for disabling the l1 cache while the l2 cache remains enabled.
chapter 9 cache organization 213 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 9.5 l2 cache testing the AMD-K6-IIIE+ processor provides the l2aar msr that allows for direct access to the l2 cache and l2 tag arrays. for more detailed information, refer to l2 cache and tag array testing on page 264. 9.6 cache-line fills the processor performs a cache-line fill for any area of system memory defined as cacheable. if an area of system memory is not explicitly defined as uncacheable by the software or system logic, or implicitly treated as uncacheable by the processor, then the memory access is assumed to be cacheable. software can prevent caching of certain pages by setting the pcd bit in the pde or pte. additionally, software can define regions of memory as uncacheable or write combinable by programming the mtrrs in the uwccr msr (see memory type range registers on page 231). write-combinable memory is defined as uncacheable. the system logic also has control of the cacheability of bus cycles. if it determines the address is not cacheable, system logic negates the ken# signal when asserting the first brdy# or na# of a cycle. the processor does not cache certain memory accesses such as locked operations. in addition, the processor does not cache pde or pte memory reads in the l1 cache (referred to as page table walks ). however, page table walks are cached in the l2 cache if the pde or pte is determined to be cacheable. when the processor needs to read memory, the processor drives a read cycle onto the bus. if the cycle is cacheable, the processor asserts cache#. if the cycle is not cacheable, a non-burst, single-transfer read takes place. the processor waits for the system logic to return the data and assert a single brdy# (see figure 60 on page 159). if the cycle is cacheable, the processor executes a 32-byte burst read cycle. the processor expects a total of four brdy# signals for a burst read cycle to take place (see figure 62 on page 163).
214 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information cache-line fills initiate 32-byte burst read cycles from memory on the system bus for the l1 instruction cache and the l1 data cache. all l1 cache-line fills supplied from the system bus are also filled in the l2 cache. 9.7 cache-line replacements as programs execute and task switches occur, some cache lines eventually require replacement. when a cache miss occurs in the l1 cache, the required cache line is filled from either the l2 cache, if the cache line is present (l2 cache hit), or from external memory, if the cache line is not present (l2 cache miss). if the cache line is filled from external memory, the cache line is filled in both the l1 and the l2 caches. two forms of cache misses and associated cache fills can take placea tag-miss cache fill and a tag-hit cache fill. n in the case of a tag-miss cache fill, the level-one cache miss is due to a tag mismatch, in which case the required cache line is filled either from the level-two cache or from external memory, and the level-one cache line within the sector that was not required is marked as invalid. n in the case of a tag-hit cache fill, the address matches the tag, but the requested cache line is marked as invalid. the required level-one cache line is filled from the level-two cache or from external memory, and the level-one cache line within the sector that is not required remains in the same cache state. if a l1 data-cache line being filled replaces a modified line, the modified line is written back to the l2 cache if the cache line is present (l2 cache hit). by design, if a cache line is in the modified state in the l1 cache, this cache line can only exist in the l2 cache in the exclusive state. during the writeback, the l2 cache-line state is changed from exclusive to modified, and the writeback does not occur on the system bus. if the replacement writeback does not hit the l2 cache (l2 cache miss), then the modified l1 cache line is written back on the system bus, and the l2 cache is not updated. if the other cache line in this sector is in the modified state, it is also written back in the same manner.
chapter 9 cache organization 215 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information l1 instruction-cache lines and l2 cache lines are replaced using a least recently used (lru) algorithm. if a line replacement is required, lines are replaced when read cache misses occur. the l1 data cache uses a slightly different approach to line replacement. if a miss occurs, and a replacement is required, lines are replaced by using a least recently allocated (lra) algorithm. 9.8 write allocate write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 data cache. if the line does not exist in the l2 cache, the processor performs a 32-byte burst read cycle on the system bus to fetch the data-cache line addressed by the pending write cycle. if the line does exist in the l2 cache, the data is supplied directly from the l2 cache, in which case a system bus cycle is not executed. the data associated with the pending write cycle is merged with the recently-allocated data-cache line and stored in the processors l1 data cache. if the data-cache line was fetched from memory (because of a l2 cache miss), the data is stored, without modification, in the l2 cache. the final mesi state of the cache lines depends on the state of the wb/wt# and pwt signals during the burst read cycle and the subsequent l1 data cache write hit (see table 39 on page 221 to determine the cache-line states and the access types following a cache write miss). if the l1 data cache line is stored in the modified state, then the same cache line is stored in the l2 cache in the exclusive state. if the l1 data cache line is stored in the shared state, then the same cache line is stored in the l2 cache in the shared state. if a data-cache line fetch from memory is attempted because the write allocate misses the l2 cache, and ken# is sampled negated, the processor does not perform an allocation. in this case, the pending write cycle is executed as a single write cycle on the system bus. during write allocates that miss the l2 cache, a 32-byte burst read cycle is executed in place of a non-burst write cycle. while the burst read cycle generally takes longer to execute than the non-burst write cycle, performance gains are realized on subsequent write cycle hits to the write-allocated cache line.
216 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information due to the nature of software, memory accesses tend to occur in proximity of each other (principle of locality). the likelihood of additional write hits to the write-allocated cache line is high. write allocates that hit the l2 cache increase performance by avoiding accesses to the system bus. the following is a description of three mechanisms by which the AMD-K6-IIIE+ processor performs write allocations. a write allocate is performed when any one or more of these mechanisms indicates that a pending write is to a cacheable area of memory. write to a cacheable page every time the processor completes a l1 cache line fill, the address of the page in which the cache line resides is saved in the cacheability control register (ccr). the page address of subsequent write cycles is compared with the page address stored in the ccr. if the two addresses are equal, then the processor performs a write allocate because the page has already been determined to be cacheable. when the processor performs a l1 cache line fill from a different page than the address saved in the ccr, the ccr is updated with the new page address. write to a sector if the address of a pending write cycle matches the tag address of a valid l1 cache sector, but the addressed cache line within the sector is marked invalid (a sector hit but a cache line miss), then the processor performs a write allocate. the pending write cycle is determined to be cacheable because the sector hit indicates the presence of at least one valid cache line in the sector. the two cache lines within a sector are guaranteed by design to be within the same page. write allocate limit the AMD-K6-IIIE+ processor uses two mechanisms that are programmable within the write handling control register (whcr) to enable write allocations for write cycles that address a definable area, or a special 1-mbyte memory area. the whcr contains two fieldsthe write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 84).
chapter 9 cache organization 217 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 84. write handling control register (whcr) write allocate enable limit field. the waelim field is 10 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that misses the l1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector. the maximum value of this limit is ((2 10 C1) 4 mbytes) = 4092 mbytes. when all the bits in this field are set to 0, all memory is above this limit and write allocates due to this mechanism is disabled (even if all bits in the waelim field are set to 0, write allocates can still occur due to the write to a cacheable page and write to a sector mechanisms). write allocate enable 15-to-16-mbyte bit. the write allocate enable 15-to-16-mbyte (wae15m) bit is used to enable write allocations for memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 1 to allow write allocate in this memory area. this bit is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0 (even if the wae15m bit is set to 0, write allocates can still occur between 15 mbytes and 16 mbytes due to the write to a cacheable page and write to a 15 22 0 63 reserved waelim 16 notes : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits waelim write allocate enable limit 31-22 wae15m write allocate enable 15-to-16-mbyte 16 17 21 31 32
218 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information sector mechanisms). the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition a write allocate is not performed in the memory area between 640 kbytes and 1 mbyte unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanismswrite to a cacheable page and write to a sector. it is not considered safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a noncacheable region of memory. if a memory region is defined as write combinable or uncacheable by a mtrr, write allocates are not performed in that region. write allocate logic mechanisms and conditions figure 85 shows the logic flow for all the mechanisms involved with write allocate for memory bus cycles. the left side of the diagram (the text) describes the conditions that need to be true in order for the value of that line to be a 1. items 1 to 4 of the diagram are related to general cache operation and items 5 to 10 are related to the write allocate mechanisms. for more information about write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326. figure 85. write allocate logic mechanisms and conditions 1) cd bit of cr0 perform write allocate 3) ci bit of tr12 2) pcd signal 5) write to cacheable page (ccr) 6) write to a sector 8) between 640 kbytes and 1 mbyte 7) less than limit (waelim) 9) between 15C16 mbytes 10) write allocate enable 15C16 mbyte (wae15m) 4) uc or wc
chapter 9 cache organization 219 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information the following list describes the corresponding items in figure 85: 1. cd bit of cr0 when the cache disable (cd) bit within con- trol register 0 (cr0) is set to 1, the cache fill mechanism for both reads and writes is disabled and write allocate does not occur. 2. pcd signal when the pcd (page cache disable) signal is driven high, caching for that page is disabled, even if ken# is sampled asserted, and write allocate does not occur. 3. ci bit of tr12 when the cache inhibit bit of test register 12 is set to 1, l1 and l2 cache fills are disabled and write allocate does not occur. 4. uc or wc if a pending write cycle addresses a region of memory defined as write combinable or uncacheable by an mtrr, write allocates are not performed in that region. 5. write to a cacheable page (ccr) a write allocate is performed if the processor knows that a page is cacheable. the ccr is used to store the page address of the last l1 cache fill for a read miss. see write to a cacheable page on page 216 for a detailed description of this condition. 6. write to a sector a write allocate is performed if the address of a pending write cycle matches the tag address of a valid l1 cache sector but the addressed cache line within the sector is invalid. see write to a sector on page 216 for a detailed description of this condition. 7. less than limit (waelim) the write allocate limit mechanism determines if the memory area being addressed is less than the limit set in the waelim field of whcr. if the address is less than the limit, write allocate for that memory address is performed as long as conditions 8 through 10 do not prevent write allocate (even if conditions 8 and 10 attempt to prevent write allocate, condition 5 or 6 allows write allocate to occur). 8. between 640 kbytes and 1 mbyte write allocate is not performed in the memory area between 640 kbytes and 1 mbyte. it is not considered safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because this area of memory is considered a noncacheable region of memory (even if condition 8 attempts to prevent write allocate, condition 5 or 6 allows write allocate to occur).
220 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 9. between 15C16 mbytes if the address of a pending write cycle is in the 1 mbyte of memory between 15 mbytes and 16 mbytes, and the wae15m bit is set to 1, write allocate for this cycle is enabled. 10. write allocate enable 15C16 mbytes (wae15m) this condition is associated with the write allocate limit mechanism and affects write allocate only if the limit specified by the waelim field is greater than or equal to 16 mbytes. if the memory address is between 15 mbytes and 16 mbytes, and the wae15m bit in the whcr is set to 0, write allocate for this cycle is disabled (even if condition 10 attempts to prevent write allocate, condition 5 or 6 allows write allocate to occur). 9.9 prefetching hardware prefetching the AMD-K6-IIIE+ processor conditionally performs cache prefetching, which results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. from the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. the burst read cycles do not occur back-to-back (wait states occur) if the processor is not ready to start a new cycle, if higher priority data read or write requests exist, or if na# (next address) was sampled negated. wait states can also exist between burst cycles if the processor samples ahold or boff# asserted. software prefetching the 3dnow! technology includes an instruction called prefetch that allows a cache line to be prefetched into the l1 data cache and the l2 cache. unlike prefetching under hardware control, software prefetching only fetches the cache line specified by the operand of the prefetch instruction, and does not attempt to fetch the other cache line in the sector. the prefetch instruction format is defined in table 15, 3dnow!? instructions, on page 89. for more detailed information, see the 3dnow!? technology manual , order# 21928.
chapter 9 cache organization 221 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 9.10 cache states table 39 shows all the possible cache-line states before and after program-generated accesses to individual cache lines. table 39. l1 and l2 cache states for read and write accesses type cache state before access 1 access type cache state after access mesi state 2 l1 l2 l1 l2 cache read read miss l1, read miss l2 i i single read from bus i i i i burst read from bus, fill l1 and l2 3 s or e 4 s or e 4 read hit l1 e CC e C sCC sC mCC mC read miss l1, read hit l2 i e fill l1 e e i s fill l1 s s i m fill l1 m e i m fill l1 e 5 m 5 cache write write miss l1 write miss l2 ii single write to bus 6 ii ii burst read from bus, fill l1 and l2, write to l1 7 m 8 e 8 ii burst read from bus, fill l1 and l2, write to l1 and l2, single write to bus 7 s 9 s 9 write hit l1 si write to l1, single write to bus s or e 4 i ss write to l1 and l2, single write to bus s or e 4 s or e 4 e or m C write to l1 m C write miss l1 write hit l2 ie write to l2 6 im is write to l2, single write to bus 6 i s or e 4 im write to l2 6 im ie fill l1, write to l1 7 me is write to l2, single write to bus 7 s or e 4 s or e 4 im fill l1, write to l1 7 me notes: 1. m = modified, e = exclusive, s = shared, i = invalid. the exclusive and shared states are indistinguishable in the l1 instruc tion cache and are treated as valid states. 2. the final mesi state assumes that the state of the wb/wt# signal remains the same for all accesses to a particular cache line . 3. if cache# is driven low and ken# is sampled asserted. 4. if pwt is driven low and wb/wt# is sampled high, the line is cached in the exclusive (writeback) state. if pwt is driven high or wb/wt# is sampled low, the line is cached in the shared (writethrough) state.
222 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 9.11 cache coherency different ways exist to maintain coherency between the system memory and cache memories. inquire cycles, internal snoops, flush#, wbinvd, invd, and line replacements all prevent inconsistencies between memories. inquire cycles inquire cycles are bus cycles initiated by system logic that ensure coherency between the caches and main memory. in systems with multiple bus masters, system logic maintains cache coherency by driving inquire cycles to the processor. system logic initiates inquire cycles by asserting ahold, boff#, or hold to obtain control of the address bus and then driving eads#, inv (optional), and an inquire address (a[31:5]). this type of bus cycle causes the processor to compare the tags for its l1 instruction and l1 data caches, and l2 cache, with the inquire address. n if there is a hit to a shared or exclusive line in the l1 data cache or the l2 cache, or a valid line in the l1 instruction cache, the processor asserts hit#. n if the compare hits a modified line in the l1 data cache or the l2 cache, the processor asserts hit# and hitm#. if hitm# is asserted, the processor writes the modified line back to memory. n if inv was sampled asserted with eads#, a hit invalidates the line. n if inv was sampled negated with eads#, a hit leaves the line in the shared state or transitions it from the exclusive or modified state to the shared state. table 40 on page 225 lists valid combinations of mesi states permitted for a cache line in the l1 and l2 caches, and shows the effects of inquire cycles performed with inv equal to 0 (non-invalidating) and inv equal to 1 (invalidating). 5. this entry only applies to the l1 instruction cache. by design, a cache line cannot exist in the exclusive state in the l1 da ta cache and in the modified state in the l2 cache. 6. assumes the write allocate conditions as specified in write allocate on page 215 are not met. 7. assumes the write allocate conditions as specified in write allocate on page 215 are met. 8. assumes pwt is driven low and wb/wt# is sampled high. 9. assumes pwt is driven high or wb/wt# is sampled low. not applicable or none.
chapter 9 cache organization 223 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information internal snooping internal snooping is initiated by the processor (rather than system logic) during certain cache accesses. it is used to maintain coherency between the l1 instruction cache and the l1 data cache. the processor automatically snoops its l1 instruction cache during read or write misses to its l1 data cache, and it snoops its l1 data cache during read misses to its l1 instruction cache. the l2 cache is not snooped during misses to either of the l1 caches. table 41 on page 226 summarizes the actions taken during this internal snooping. if an internal snoop hits its target, the processor does the following: n l1 data cache snoop during an l1 instruction-cache read miss if modified, the line in the l1 data cache is written back. if the writeback hits the l2 cache, the cache line is stored in the l2 cache in the modified state and no writeback occurs on the system bus. if the writeback misses the l2 cache, the cache line is written back on the system bus to external memory. regardless of its state, the l1 data-cache line is invalidated and the l1 instruction cache performs a read from either the l2 cache (if a l2 hit occurs) or external memory (if a l2 miss occurs). n l1 instruction cache snoop during an l1 data cache miss the line in the instruction cache is marked invalid, and the l1 data-cache read or write is performed as defined in table 39 on page 221. flush# in response to sampling flush# asserted, the processor writes back any l1 data cache lines and l2 cache lines that are in the modified state and then marks all lines in the l1 instruction cache, the l1 data cache, and the l2 cache as invalid. page flush/invalidate register (pfir) the AMD-K6-IIIE+ processor contains the page flush/invalidate register (pfir) that allows cache invalidation and optional flushing of a specific 4-kbyte page from the linear address space (see figure 86 on page 224). when the pfir is written to (using the wrmsr instruction), the invalidation and, optionally, the flushing begins. the total amount of cache in the AMD-K6-IIIE+ processor is 320 kbytes. using this register can result in a much lower cycle count for flushing particular pages versus flushing the entire cache.
224 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 86. page flush/invalidate register (pfir) linpage field. this 20-bit field must be written with bits 31:12 of the linear address of the 4-kbyte page that is to be invalidated and optionally flushed from the l1 or the l2 cache. pf bit. if an attempt to invalidate or flush a page results in a page fault, the processor sets the pf bit to 1, and the invalidate or flush operation is not performed (even though invalidate operations do not normally generate page faults). in this case, an actual page fault exception is not generated. if the pf bit equals 0 after an invalidate or flush operation, then the operation executed successfully. the pf bit must be read after every write to the pfir register to determine if the invalidate or flush operation executed successfully. f/i bit. this bit is used to control the type of action that occurs to the specified linear page. if a 0 is written to this bit, the operation is a flush, in which case all cache lines in the modified state within the specified page are written back to memory, after which the entire page is invalidated. if a 1 is written to this bit, the operation is an invalidation, in which case the entire page is invalidated without the occurrence of any writebacks. wbinvd and invd these x86 instructions cause all cache lines to be marked as invalid. wbinvd writes back modified lines before marking all cache lines invalid. invd does not write back modified lines. cache-line replacement replacing lines in the l1 cache and the l2 cache, according to the line replacement algorithms described in cache-line fills on page 213, ensures coherency between external memory and the caches. linpage 10 63 f / i reserved symbol description bit linpage 20-bit linear page address 31-12 pf page fault occurred 8 f/i flush/invalidate command 0 11 31 12 32 p f 987
chapter 9 cache organization 225 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 40 shows all possible cache-line states before and after inquire cycles. table 40. valid l1 and l2 cache states and effect of inquire cycles cache state before inquire 1 notes: 1. m = modified, e = exclusive, s = shared, i = invalid. the exclusive and shared states are indistinguishable in the l1 instruc tion cache and are treated as valid states. memory access 2 2. writeback cycles to the bus are 32-byte burst writes. cache state after inquire inv = 0 inv = 1 l1 l2 l1 l2 l1 l2 i m writeback l2 to bus i s i i ie Cisii isC isii iiC iiii e 3 3. this entry only applies to the l1 instruction cache. by design, a cache line cannot exist in the exclusive state in the l1 da ta cache and in the modified state in the l2 cache. m 3 writeback l2 to bus s s i i eeC ssii eiC siii m e writeback l1 to bus s i i i m i writeback l1 to bus s i i i ssC ssii siC siii
226 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 41 shows all possible cache-line states before and after various cache-related operations. table 41. l1 and l2 cache states for snoops, flushes, and invalidation operation type cache state before operation 1 notes: 1. m = modified, e = exclusive, s = shared, i = invalid. the exclusive and shared states are indistinguishable in the l1 instruc tion cache and are treated as valid states. access type 2 2. writeback cycles to the bus are 32-byte burst writes. cache state after operation l1 l2 l1 l2 internal snoop im Cim ieC ie isC is iiC ii e 3 3. this entry only applies to the l1 instruction cache. by design, a cache line cannot exist in the exclusive state in the l1 da ta cache and in the modified state in the l2 cache. not applicable or none. m 3 Cim eeC ie eiC ii m e writeback l1 to l2 i m m i writeback l1 to bus i i ssC is siC ii flush# signal s or e C i i m C writeback l1 to bus i i C m writeback l2 to bus i i pfir (f/i = 0) s or e C i i m C writeback l1 to bus i i C m writeback l2 to bus i i pfir (f/i = 1) C C C i i wbinvd instruction s or e C i i m C writeback l1 to bus i i C m writeback l2 to bus i i invd instruction C C C i i
chapter 9 cache organization 227 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 9.12 writethrough and writeback coherency states the terms writethrough and writeback apply to two related concepts in a read-write cache like the AMD-K6-IIIE+ processor l1 data cache and the l2 cache. the following conditions apply to both the writethrough and writeback modes: n memory writes a relationship exists between external memory writes and their concurrence with cache updates: ? an external memory write that occurs concurrently with a cache update to the same location is a writethrough . writethroughs are driven as single cycles on the bus. ? an external memory write that occurs after the processor has modified a cache line is a writeback . writebacks are driven as burst cycles on the bus. n coherency state a relationship exists between mesi coherency states and writethrough-writeback coherency states of lines in the cache as follows: ? shared and invalid mesi lines are in the writethrough state. ? modified and exclusive mesi lines are in the writeback state. 9.13 a20m# masking of cache accesses although the processor samples a20m# as a level-sensitive input on every clock edge, it should only be asserted in real mode. the processor applies the a20m# masking to its tags, through which all programs access the caches. therefore, assertion of a20m# affects all addresses (cache and external memory), including the following: n cache-line fills (caused by read misses or write allocates) n cache writethroughs (caused by write misses or write hits to lines in the shared state) however, a20m# does not mask writebacks or invalidations caused by the following actions: n internal snoops n inquire cycles n the flush# signal
228 cache organization chapter 9 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information n writing to the page flush/invalidate register (pfir) n the wbinvd instruction
chapter 10 write merge buffer 229 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 10 write merge buffer the AMD-K6-IIIE+ processor contains an 8-byte write merge buffer that allows the processor to conditionally combine data from multiple noncacheable write cycles into this merge buffer. the merge buffer operates in conjunction with the memory type range registers (mtrrs). refer to memory type range registers on page 231 for a description of the mtrrs. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. 10.1 ewb e# control the presence of the merge buffer creates the potential to perform out-of-order write cycles relative to the processors caches. in general, the ordering of write cycles that are driven externally on the system bus and those that hit the processors cache can be controlled by the ewbe# signal. see ewbe# (external write buffer empty) on page 110 for more information. if ewbe# is sampled negated, the processor delays the commitment of write cycles to cache lines in the modified state or exclusive state in the processors caches. therefore, the system logic can enforce strong ordering by negating ewbe# until the external write cycle is complete, thereby ensuring that a subsequent write cycle that hits a cache does not complete ahead of the external write cycle. however, the addition of the write merge buffer introduces the potential for out-of-order write cycles to occur between writes to the merge buffer and writes to the processors caches. because these writes occur entirely within the processor and are not sent out to the processor bus, the system logic is not able to enforce strong ordering with the ewbe# signal. the ewbe# control (ewbec) bits in the efer register provide a mechanism for enforcing three different levels of write ordering in the presence of the write merge buffer:
230 write merge buffer chapter 10 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information n efer[3] is defined as the global ewbe# disable (gewbed). when gewbed equals 1, the processor does not attempt to enforce any write ordering internally or externally (the ewbe# signal is ignored). this is the maximum performance setting. n efer[2] is defined as the speculative ewbe# disable (sewbed). sewbed only affects the processor when gewbed equals 0. if gewbed equals 0 and sewbed equals 1, the processor enforces strong ordering for all internal write cycles with the exception of write cycles addressed to a range of memory defined as uncacheable (uc) or write-combining (wc) by the mtrrs. in addition, the processor samples the ewbe# signal. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting provides performance comparable to, but slightly less than, the performance obtained when gewbed equals 1 because some degree of write ordering is maintained. n if gewbed equals 0 and sewbed equals 0, the processor enforces strong ordering for all internal and external write cycles. in this setting, the processor assumes, or speculates , that strong order must be maintained between writes to the merge buffer and writes that hit the processors caches. once the merge buffer is written out to the processors bus, the ewbe# signal is sampled. if ewbe# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until ewbe# is sampled asserted. this setting is the default after reset and provides the lowest performance of the three settings because full write ordering is maintained.
chapter 10 write merge buffer 231 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 42 summarizes the three settings of the ewbec field for the efer register, along with the effect of write ordering and performance. for more information on the efer register, see extended feature enable register (efer) on page 47. 10.2 memory type range registers the AMD-K6-IIIE+ processor provides two variable-range memory type range registers (mtrrs)mtrr0 and mtrr1that each specify a range of memory. each range can be defined as one of the following memory types: n uncacheable (uc) memory memory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. memory write cycles are targeted at the specified memory address and a write allocation does not occur. n write-combining (wc) memory memory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. the processor conditionally combines data from multiple noncacheable write cycles that are addressed within this range into a merge buffer. merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. this memory type is applicable for linear video frame buffers. table 42. ewbec settings and performance efer[3] (gewbed) efer[2] (sewbed) write ordering performance 1 0 or 1 none best 0 1 all except uc/wc close-to-best 0 0 all slowest
232 write merge buffer chapter 10 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information uc/wc cacheability control register (uwccr) the mtrrs are accessed by addressing the 64-bit msr known as the uc/wc cacheability control register (uwccr). the msr address of the uwccr is c000_0085h. following reset, all bits in the uwccr register are set to 0. mtrr0 (lower 32 bits of the uwccr register) defines the size and memory type of range 0 and mtrr1 (upper 32 bits) defines the size and memory type of range 1 (see figure 87). . figure 87. uc/wc cacheability control register (uwccr) physical base address n (n=0, 1). this address is the 15 most- significant bits of the physical base address of the memory range. the least-significant 17 bits of the base address are not needed because the base address is by definition always aligned on a 128-kbyte boundary. physical address mask n (n=0, 1). this value is the 15 most- significant bits of a physical address mask that is used to define the size of the memory range. this mask is logically anded with both the physical base address field of the uwccr register and the physical address generated by the processor. if the results of the two and operations are equal, then the generated physical address is considered within the range. that is, if: mask & physical base address = mask & physical address generated then, the physical address generated by the processor is in the range. 16 0 63 physical address mask 0 17 31 physical base address 0 1 2 physical address mask 1 physical base address 1 32 33 34 48 49 u c 0 w c 0 u c 1 w c 1 mtrr1 mtrr0 symbol description bits uc0 uncacheable memory type 0 wc0 write-combining memory type 1 symbol description bits uc1 uncacheable memory type 32 wc1 write-combining memory type 33
chapter 10 write merge buffer 233 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information wcn (n=0, 1). when set to 1, this memory range is defined as write combinable (see table 43). write-combinable memory is uncacheable. ucn (n=0, 1). when set to 1, this memory range is defined as uncacheable (see table 43). 10.3 memory-range restrictions the following rules regarding the address alignment and size of each range must be adhered to when programming the physical base address and physical address mask fields of the uwccr register: n the minimum size of each range is 128 kbytes. n the physical base address must be aligned on a 128-kbyte boundary. n the physical base address must be range-size aligned . for example, if the size of the range is 1 mbyte, then the physical base address must be aligned on a 1-mbyte boundary. n all bits set to 1 in the physical address mask must be contiguous. likewise, all bits set to 0 in the physical address mask must be contiguous. for example: 111_1111_1100_0000b is a valid physical address mask. 111_1111_1101_0000b is invalid. table 43. wc/uc memory type wcn ucn memory type 0 0 no effect on cacheability or write combining 1 0 write-combining memory range (uncacheable) 0 or 1 1 uncacheable memory range
234 write merge buffer chapter 10 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 44 lists the valid physical address masks and the resulting range sizes that can be programmed in the uwccr register. table 44. valid masks and range sizes for uwccr register masks size 111_1111_1111_1111b 128 kby tes 111_1111_1111_1110b 256 kbytes 111_1111_1111_1100b 512 kby tes 111_1111_1111_1 000b 1 mbyte 111_1111_1111_0 000b 2 mbytes 111_1111_1110_0 000b 4 mbytes 111_1111_1100_0 000b 8 mbytes 111_1111_1000_0 000b 16 mbytes 111_1111_0000_0 000b 32 mbytes 111_1110_0000_0 000b 64 mbytes 111_1100_0000_0000b 128 mbytes 111_1000_0000_0000b 256 mbytes 111_0000_0000_0000b 512 mbytes 110_0000_0000_0000b 1 gbyte 100_0000_0000_0000b 2 gbytes 000_0000_0000_0000b 4 gbytes
chapter 10 write merge buffer 235 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 10.4 examples suppose that the range of memory from 16 mbytes to 32 mbytes is uncacheable, and the 8-mbyte range of memory on top of 1 gbyte is write-combinable. range 0 is defined as the uncacheable range, and range 1 is defined as the write- combining range. n extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 16 mbytes (0100_0000h) yields a physical base address 0 field of 000_0000_1000_0000b. because the uncacheable range size is 16 mbytes, the physical mask value 0 field is 111_1111_1000_0000b, according to table 44 on page 234. bit 1 of the uwccr register (wc0) is set to 0 and bit 0 of the uwccr register is set to 1 (uc0). n extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 1 gbyte (4000_0000h) yields a physical base address 1 field of 010_0000_0000_0000b. because the write-combining range size is 8 mbytes, the physical mask value 1 field is 111_1111_1100_0000b, according to table 44 on page 234. bit 33 of the uwccr register (wc1) is set to 1 and bit 32 of the uwccr register is set to 0 (uc1).
236 write merge buffer chapter 10 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 11 floating-point and multimedia execution units 237 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 11 floating-point and multimedia execution units 11.1 floating-point execution unit the AMD-K6-IIIE+ processor contains an ieee 754-compatible and 854-compatible floating-point execution unit designed to accelerate the performance of software that utilizes the x86 floating-point instruction set. floating-point software is typically written to manipulate numbers that are very large or very small, that require a high degree of precision, or that result from complex mathematical operations such as transcendentals. applications that take advantage of floating-point operations include geometric calculations for graphics acceleration, scientific, statistical, and engineering applications, and business applications that use large amounts of high-precision data. the high-performance floating-point execution unit contains an adder unit, a multiplier unit, and a divide/square root unit. these low-latency units can execute floating-point instructions in as few as two processor clocks. to increase performance, the processor is designed to simultaneously decode most floating-point instructions with most short-decodeable instructions. see software environment on page 27 for a description of the floating-point data types, registers, and instructions. handling floating-point exceptions the AMD-K6-IIIE+ processor provides the following two types of exception handling for floating-point exceptions: n if the numeric error (ne) bit in cr0 is set to 1, the processor invokes the interrupt 10h handler. in this manner, the floating-point exception is completely handled by software. n if the ne bit in cr0 is set to 0, the processor requires external logic to generate an interrupt on the intr signal in order to handle the exception.
238 floating-point and multimedia execution units chapter 11 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information external logic support of floating-point exceptions the processor provides the ferr# (floating-point error) and ignne# (ignore numeric error) signals to allow the external logic to generate the interrupt in a manner consistent with ibm-compatible pc/at systems. the assertion of ferr# indicates the occurrence of an unmasked floating-point exception resulting from the execution of a floating-point instruction. ignne# is used by the external hardware to control the effect of an unmasked floating-point exception. under certain circumstances, if ignne# is sampled asserted, the processor ignores the floating-point exception. figure 88 on page 239 illustrates an implementation of external logic for supporting floating-point exceptions. the following example explains the operation of the external logic in figure 88: 1. as the result of a floating-point exception, the processor asserts ferr#. 2. the assertion of ferr# and the sampling of ignne# negated indicates the processor has stopped instruction execution and is waiting for an interrupt. 3. the assertion of ferr# leads to the assertion of intr by the interrupt controller. 4. the processor acknowledges the interrupt and jumps to the corresponding interrupt service routine in which an i/o write cycle to address port f0h leads to the assertion of ignne#. 5. when ignne# is sampled asserted, the processor ignores the floating-point exception and continues instruction execution. 6. when the processor negates ferr#, the external logic negates ignne#. see ferr# (floating-point error) on page 111 and ignne# (ignore numeric exception) on page 116 for more details.
chapter 11 floating-point and multimedia execution units 239 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 88. external logic for supporting floating-point exceptions 11.2 multimedia and 3dnow!? execution units the multimedia and 3dnow! execution units of the AMD-K6-IIIE+ processor are designed to accelerate the performance of software written using the industry-standard mmx instructions and the new 3dnow! instructions. applications that can take advantage of the mmx and 3dnow! instructions include graphics, video and audio compression and decompression, speech recognition, and telephony applications. 3dnow! technology enables fast frame rates on high-resolution 3d-rendered scenes, realistic physical modeling of real-world environments, sharp and detailed 3d imaging, smooth video playback, and theater-quality audio. the AMD-K6-IIIE+ processor supports five new digital signal processing (dsp) instructions, developed to enhance the performance of communications applications, including soft xdsl modems, mp3 recording, and dolby digital and surround sound processing. for more information on mmx instructions, see the amd-k6 ? processor multimedia technology manual , order# 20726. for ferr# flip-flop clock q data q clear irq13 interrupt controller i/o address port f0h amd-k6- iii e+ processor ferr# intr ignne# reset 1 ignne# flip-flop clock q data q clear
240 floating-point and multimedia execution units chapter 11 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information more information on 3dnow! instructions, see the 3dnow!? technology manual , order# 21928. for more information on the 3dnow! technology dsp extensions, see the amd extensions to the 3dnow!? and mmx? instructions sets manual , order# 22466. the multimedia execution unit can execute mmx instructions in a single processor clock. all mmx and 3dnow! arithmetic instructions are pipelined for higher performance. to increase performance, the processor is designed to simultaneously decode all mmx and 3dnow! instructions with most other instructions. 11.3 floating-point and mmx?/3dnow!? instruction compatibility registers the eight 64-bit mmx registers (which are also utilized by 3dnow! instructions) are mapped on the floating-point stack. this enables backward compatibility with all existing software. for example, the register saving event that is performed by operating systems during task switching requires no changes to the operating system. the same support provided in an operating systems interrupt 7 handler (device not available) for saving and restoring the floating-point registers also supports saving and restoring the mmx registers. exceptions there are no new exceptions defined for supporting the mmx and 3dnow! instructions. all exceptions that occur while decoding or executing an mmx or 3dnow! instruction are handled in existing exception handlers without modification. ferr# and ignne# mmx instructions and 3dnow! instructions do not generate floating-point exceptions. however, if an unmasked floating-point exception is pending, the processor asserts ferr# at the instruction boundary of the next floating-point instruction, mmx instruction, 3dnow! instruction or wait instruction. the sampling of ignne# asserted only affects processor operation during the execution of an error-sensitive floating-point instruction, mmx instruction, 3dnow! instruction or wait instruction when the ne bit in cr0 is set to 0.
chapter 12 system management mode (smm) 241 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 12 system management mode (smm) smm is an alternate operating mode entered by way of a system management interrupt (smi#) and handled by an interrupt service routine. smm is designed for system control activities such as power management. these activities appear transparent to conventional operating systems like dos and windows. smm is targeted for use by the basic input output system (bios), specialized low-level device drivers, and the operating system. the code and data for smm are stored in the smm memory area, which is isolated from main memory. the processor enters smm by the assertion of the smi# interrupt and the processors acknowledgment by the assertion of smiact#. at this point the processor saves its state into the smm memory state-save area and jumps to the smm service routine. the processor returns from smm when it executes the resume (rsm) instruction from within the smm service routine. subsequently, the processor restores its state from the smm save area, negates smiact#, and resumes execution with the instruction following the point where it entered smm. the following sections summarize the smm state-save area, entry into and exit from smm, exceptions and interrupts in smm, memory allocation and addressing in smm, and the smi# and smiact# signals. 12.1 smm operating mode and default register values the software environment within smm has the following characteristics: n addressing and operation in real mode n 4-gbyte segment limits n default 16-bit operand, address, and stack sizes, although instruction prefixes can override these defaults n control transfers that do not override the default operand size truncate the eip to 16 bits n far jumps or calls cannot transfer control to a segment with a base address requiring more than 20 bits, as in real mode segment-base addressing
242 system management mode (smm) chapter 12 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information n a20m# is masked n interrupt vectors use the real-mode interrupt vector table n the if flag in eflags is cleared (intr not recognized) n the tf flag in eflags is cleared n the nmi and init interrupts are disabled n debug register dr7 is cleared (debug traps disabled) figure 89 shows the default map of the smm memory area. it consists of a 64-kbyte area, between 0003_0000h and 0003_ffffh, of which the top 32 kbytes (0003_8000h to 0003_ffffh) must be populated with ram. the default code-segment (cs) base address for the areacalled the smm base addressis at 0003_0000h. the top 512 bytes (0003_fe00h to 0003_ffffh) contain a fill-down smm state-save area. the default entry point for the smm service routine is 0003_8000h. figure 89. smm memory smm state-save area smm base address (cs) service routine entry point fill down smm service routine 32-kbyte minimum ram 0003_8000h 0003_fe00h 0003_ffffh 0003_0000h
chapter 12 system management mode (smm) 243 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 45 shows the initial state of registers when entering smm. 12.2 smm state-save area when the processor acknowledges an smi# interrupt by asserting smiact#, it saves its state in a 512-byte smm state-save area shown in table 46. the save begins at the top of the smm memory area (smm base address + ffffh) and fills down to smm base address + fe00h. table 46 shows the offsets in the smm state-save area relative to the smm base address. the smm service routine can alter any of the read/write values in the state-save area. table 45. initial state of registers in smm registers smm initial state general purpose registers unmodified eflags 0000_0002h cr0 pe, em, ts, and pg are cleared (bits 0, 2, 3, and 31). the other bits are unmodified. dr7 0000_0400h gdtr, ldtr, idtr, tssr, dr6 unmodified eip 0000_8000h cs 0003_0000h ds, es, fs, gs, ss 0000_0000h table 46. smm state-save area map address offset contents saved fffch cr0 fff8h cr3 fff4h eflags fff0h eip ffech edi ffe8h esi ffe4h ebp ffe0h esp ffdch ebx ffd8h edx ffd4h ecx ffd0h eax
244 system management mode (smm) chapter 12 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information ffcch dr6 ffc8h dr7 ffc4h tr ffc0h ldtr base ffbch gs ffb8h fs ffb4h ds ffb0h ss ffach cs ffa8h es ffa4h i/o trap doubleword ffa0h no data dump at this address ff9ch i/o trap eip 1 ff98h no data dump at this address ff94h no data dump at this address ff90h idt base ff8ch idt limit ff88h gdt base ff84h gdt limit ff80h tss attr ff7ch tss base ff78h tss limit ff74h no data dump at this address ff70h ldt high ff6ch ldt low ff68h gs attr ff64h gs base ff60h gs limit ff5ch fs attr ff58h fs base ff54h fs limit ff50h ds attr ff4ch ds base ff48h ds limit ff44h ss attr ff40h ss base table 46. smm state-save area map (continued) address offset contents saved
chapter 12 system management mode (smm) 245 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 12.3 smm revision identifier the smm revision identifier at offset fefch in the smm state-save area specifies the version of smm and the extensions that are available on the processor. the smm revision identifier fields are as follows: n bits 31C18 reserved n bit 17 smm base address relocation (1 = enabled) n bit 16 i/o trap restart (1 = enabled) n bits 15C0 smm revision level for the AMD-K6-IIIE+ proces- sor= 0002h ff3ch ss limit ff38h cs attr ff34h cs base ff30h cs limit ff2ch es attr ff28h es base ff24h es limit ff20h no data dump at this address ff1ch no data dump at this address ff18h no data dump at this address ff14h cr2 ff10h cr4 ff0ch i/o restart esi 1 ff08h i/o restart ecx 1 ff04h i/o restart edi 1 ff02h halt restart slot ff00h i/o trap restart slot fefch smm revid fef8h smm base fef7hCfe00h no data dump at this address notes: 1. only contains information if smi# is asserted during a valid i/o bus cycle. table 46. smm state-save area map (continued) address offset contents saved
246 system management mode (smm) chapter 12 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 47 shows the format of the smm revision identifier. 12.4 smm base address during reset, the processor sets the base address of the code-segment (cs) for the smm memory areathe smm base addressto its default, 0003_0000h. the smm base address at offset fef8h in the smm state-save area can be changed by the smm service routine to any address that is aligned to a 32-kbyte boundary. (locations not aligned to a 32-kbyte boundary cause the processor to enter the shutdown state when executing the rsm instruction.) in some operating environments it may be desirable to relocate the 64-kbyte smm memory area to a high memory area in order to provide more low memory for legacy software. during system initialization, the base of the 64-kbyte smm memory area is relocated by the bios. to relocate the smm base address, the system enters the smm handler at the default address. this handler changes the smm base address location in the smm state-save area, copies the smm handler to the new location, and exits smm. the next time smm is entered, the processor saves its state at the new base address. this new address is used for every smm entry until the smm base address in the smm state-save area is changed or a hardware reset occurs. 12.5 halt restart slot during entry into smm, the halt restart slot at offset ff02h in the smm state-save area indicates if smm was entered from the halt state. before returning from smm, the halt restart slot (offset ff02h) can be written to by the smm service routine to specify whether the return from smm takes the processor back to the halt state or to the next instruction after the hlt instruction. table 47. smm revision identifier 31C18 17 16 15C0 reserved smm base relocation i/o trap extension smm revision level 0 1 1 0002h
chapter 12 system management mode (smm) 247 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information upon entry into smm, the halt restart slot is defined as follows: n bits 15C1 reserved n bit 0 point of entry to smm: 1 = entered from halt state 0 = not entered from halt state after entry into the smi handler and before returning from smm, the halt restart slot can be written using the following definition: n bits 15C1 reserved n bit 0 point of return when exiting from smm: 1 = return to halt state 0 = return to next instruction after the hlt instruction if the return from smm takes the processor back to the halt state, the hlt instruction is not re-executed, but the halt special bus cycle is driven on the bus after the return. 12.6 i /o trap doubleword if the assertion of smi# is recognized during the execution of an i/o instruction, the i/o trap doubleword at offset ffa4h in the smm state-save area contains information about the instruction. the fields of the i/o trap doubleword are configured as follows: n bits 31C16 i/o port address n bits 15C4 reserved n bit 3 rep (repeat) string operation (1 = rep string, 0 = not a rep string) n bit 2 i/o string operation (1 = i/o string, 0 = not an i/o string) n bit 1 valid i/o instruction (1 = valid, 0 = invalid) n bit 0 input or output instruction (1 = inx, 0 = outx)
248 system management mode (smm) chapter 12 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 48 shows the format of the i/o trap doubleword. the i/o trap doubleword is related to the i/o trap restart slot (see i/o trap restart slot). if bit 1 of the i/o trap doubleword is set by the processor, it means that smi# was asserted during the execution of an i/o instruction. the smi handler tests bit 1 to see if there is a valid i/o instruction trapped. if the i/o instruction is valid, the smi handler is required to ensure the i/o trap restart slot is set properly. the i/o trap restart slot informs the processor whether it should re-execute the i/o instruction after the rsm or execute the instruction following the trapped i/o instruction. note: if smi# is sampled asserted during an i/o bus cycle a minimum of three clock edges before brdy# is sampled asserted, the associated i/o instruction is guaranteed to be trapped by the smi handler. 12.7 i/o trap restart slot the i/o trap restart slot at offset ff00h in the smm state-save area specifies whether the trapped i/o instruction should be re-executed on return from smm. this slot in the state-save area is called the i/o instruction restart function. re-executing a trapped i/o instruction is useful, for example, if an i/o write occurs to a disk that is powered down. the system logic monitoring such an access can assert smi#. then the smm service routine would query the system logic, detect a failed i/o write, take action to power-up the i/o device, enable the i/o trap restart slot feature, and return from smm. the fields of the i/o trap restart slot are defined as follows: n bits 31C16 reserved n bits 15C0 i/o instruction restart on return from smm: 0000h = execute the next instruction after the trapped i/o instruction 00ffh = re-execute the trapped i/o instruction table 48. i/o trap doubleword configuration 3116 154 3 2 1 0 i/o port address reserved rep string operation i/o string operation valid i/o instruction input or output
chapter 12 system management mode (smm) 249 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 49 shows the format of the i/o trap restart slot. the processor initializes the i/o trap restart slot to 0000h upon entry into smm. if smm was entered due to a trapped i/o instruction, the processor indicates the validity of the i/o instruction by setting or clearing bit 1 of the i/o trap doubleword at offset ffa4h in the smm state-save area. the smm service routine should test bit 1 of the i/o trap doubleword to determine if a valid i/o instruction was being executed when entering smm and before writing the i/o trap restart slot. if the i/o instruction is valid, the smm service routine can safely rewrite the i/o trap restart slot with the value 00ffh, which causes the processor to re-execute the trapped i/o instruction when the rsm instruction is executed. if the i/o instruction is invalid, writing the i/o trap restart slot has undefined results. if a second smi# is asserted and a valid i/o instruction was trapped by the first smm handler, the processor services the second smi# prior to re-executing the trapped i/o instruction. the second entry into smm never has bit 1 of the i/o trap doubleword set, and the second smm service routine must not rewrite the i/o trap restart slot. during a simultaneous smi# i/o instruction trap and debug breakpoint trap, the AMD-K6-IIIE+ processor first responds to the smi# and postpones recognizing the debug exception until after returning from smm via the rsm instruction. if the debug registers dr3Cdr0 are used while in smm, they must be saved and restored by the smm handler. the processor automatically saves and restores dr7Cdr6. if the i/o trap restart slot in the smm state-save area contains the value 00ffh when the rsm instruction is executed, the debug trap does not occur until after the i/o instruction is re-executed. table 49. i/o trap restart slot 31C16 15C0 reserved i/o instruction restart on return from smm: 0000h = execute the next instruction after the trapped i/o 00ffh = re-execute the trapped i/o instruction
250 system management mode (smm) chapter 12 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 12.8 exceptions, interrupts, and debug in smm during an smi# i/o trap, the exception/interrupt priority of the AMD-K6-IIIE+ processor changes from its normal priority. the normal priority places the debug traps at a priority higher than the sampling of the flush# or smi# signals. however, during an smi# i/o trap, the sampling of the flush# or smi# signals takes precedence over debug traps. the processor recognizes the assertion of nmi within smm immediately after the completion of an iret instruction. once nmi is recognized within smm, nmi recognition remains enabled until smm is exited, at which point nmi masking is restored to the state it was in before entering smm.
chapter 13 test and debug 251 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 13 test and debug the AMD-K6-IIIE+ processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. in addition, the debug features of the processor allow designers to debug the instruction execution of software components. this chapter describes the following test and debug features: n built-in self-test (bist) the bist, which is invoked after the falling transition of reset, runs internal tests that exercise most on-chip ram structures. n three-state test mode a test mode that causes the processor to float its output and bidirectional pins. n boundary-scan test access port (tap) the joint test action group (jtag) test access function defined by the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. n cache inhibit a feature that disables the processors internal l1 and l2 caches. n level-2 cache array access register (l2aar) the AMD-K6-IIIE+ processor provides the l2aar that allows for direct access to the l2 cache and l2 tag arrays. n debug support consists of all x86-compatible software debug features, including the debug extensions. 13.1 built-in self-test (bist) following the falling transition of reset, the processor unconditionally runs its built-in self test (bist). the internal resources tested during bist include the following: n l1 instruction and data caches n l2 cache n instruction and data translation lookaside buffers (tlbs)
252 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the contents of the eax general-purpose register after the completion of reset indicate if the bist was successful. n if eax contains 0000_0000h, then bist was successful. n if eax is non-zero, the bist failed. following the completion of the bist, the processor jumps to address ffff_fff0h to start instruction execution, regardless of the outcome of the bist. the bist takes approximately 5,000,000 processor clocks to complete. 13.2 three-state test mode the three-state test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manufacturing testing. in this mode, the processor is electrically isolated from other components on a system board, allowing automated test equipment (ate) to test components that drive the same signals as those the processor floats. if the flush# signal is sampled low during the falling transition of reset, the processor enters the three-state test mode. (see flush# (cache flush) on page 112 for the specific sampling requirements.) the signals floated in the three-state test mode are as follows: the vcc2det, vcc2h/l#, and tdo signals are the only outputs not floated in the three-state test mode. n vcc2det and vcc2h/l# must remain low to ensure the system continues to supply the specified processor core voltage to the v cc2 pins. n a[31:3] n d/c# n m/io# n ads# n d[63:0] n pcd n adsc# n dp[7:0] n pchk# n ap n ferr# n pwt n apchk# n hit# n scyc n be[7:0]# n hitm# n smiact# n breq n hlda n vid[4:0] n cache# n lock# n w/r#
chapter 13 test and debug 253 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information n tdo is never floated because the boundary-scan test access port must remain enabled at all times, including during the three-state test mode. the three-state test mode is exited when the processor samples reset asserted. 13.3 boundary-scan test access port (tap) the boundary-scan test access port (tap) is an ieee standard that defines synchronous scanning test methods for complex logic circuits, such as boards containing a processor. the AMD-K6-IIIE+ processor supports the tap standard defined in the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. boundary scan testing uses a shift register consisting of the serial interconnection of boundary-scan cells that correspond to each i/o buffer of the processor. this non-inverting register chain, called a boundary scan register (bsr), can be used to capture the state of every processor pin and to drive every processor output and bidirectional pin to a known state. each bsr of every component on a board that implements the boundary-scan architecture can be serially interconnected to enable component interconnect testing. test access port the tap consists of the following: n test access port (tap) controller the tap controller is a synchronous, finite state machine that uses the tms and tdi input signals to control a sequence of test operations. see tap controller state machine on page 260 for a list of tap states and their definition. n instruction register (ir) the ir contains the instructions that select the test operation to be performed and the test data register (tdr) to be selected. see tap registers on page 255 for more details on the ir. n test data registers (tdr) the three tdrs are used to process the test data. each tdr is selected by an instruction in the instruction register (ir). see tap registers on page 255 for a list of these registers and their functions.
254 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information tap signals the test signals associated with the tap controller are as follows: n tck the test clock for all tap operations. the rising edge of tck is used for sampling tap signals, and the falling edge of tck is used for asserting tap signals. the state of the tms signal sampled on the rising edge of tck causes the state transitions of the tap controller to occur. tck can be stopped in the logic 0 or 1 state. n tdi the test data input represents the input to the most significant bit of all tap registers, including the ir and all test data registers. test data and instructions are serially shifted by one bit into their respective registers on the rising edge of tck. n tdo the test data output represents the output of the least significant bit of all tap registers, including the ir and all test data registers. test data and instructions are serially shifted by one bit out of their respective registers on the falling edge of tck. n tms the test mode select input specifies the test function and sequence of state changes for boundary-scan testing. if tms is sampled high for five or more consecutive clocks, the tap controller enters its reset state. n trst# the test reset signal is an asynchronous reset that unconditionally causes the tap controller to enter its reset state. refer to electrical data on page 287 and signal switching characteristics on page 297 to obtain the electrical specifications of the test signals.
chapter 13 test and debug 255 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information tap registers the AMD-K6-IIIE+ processor provides an instruction register (ir) and three test data registers (tdr) to support the boundary-scan architecture. the ir and one of the tdrsthe boundary-scan register (bsr)consist of a shift register and an output register. the shift register is loaded in parallel in the capture states. (see tap controller state machine on page 260 for a description of the tap controller states.) in addition, the shift register is loaded and shifted serially in the shift states. the output register is loaded in parallel from its corresponding shift register in the update states. instruction register (ir). the ir is a 5-bit register, without parity, that determines which instruction to run and which test data register to select. when the tap controller enters the capture-ir state, the processor loads the following bits into the ir shift register: n 01b loaded into the two least significant bits, as specified by the ieee 1149.1 standard n 000b loaded into the three most significant bits loading 00001b into the ir shift register during the capture-ir state results in loading the sample/preload instruction. for each entry into the shift-ir state, the ir shift register is serially shifted by one bit toward the tdo pin. during the shift, the most significant bit of the ir shift register is loaded from the tdi pin. the ir output register is loaded from the ir shift register in the update-ir state, and the current instruction is defined by the ir output register. see tap instructions on page 259 for a list and definition of the instructions supported by the AMD-K6-IIIE+ processor. boundary scan register (bsr). the boundary scan register is a test data register consisting of the interconnection of 152 boundary-scan cells. each output and bidirectional pin of the processor requires a two-bit cell, where one bit corresponds to the pin and the other bit is the output enable for the pin. when a 0 is shifted into the enable bit of a cell, the corresponding pin is floated, and when a 1 is shifted into the enable bit, the pin is driven valid. each input pin requires a one-bit cell that corresponds to the pin. the last cell of the bsr is reserved and does not correspond to any processor pin.
256 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the total number of bits that comprise the bsr is 297. table 50 on page 257 lists the order of these bits, where tdi is the input to bit 296, and tdo is driven from the output of bit 0. the entries listed as pin _e (where pin is an output or bidirectional signal) are the enable bits. if the bsr is the register selected by the current instruction and the tap controller is in the capture-dr state, the processor loads the bsr shift register as follows: n if the current instruction is sample/preload, then the current state of each input, output, and bidirectional pin is loaded. a bidirectional pin is treated as an output if its enable bit equals 1, and it is treated as an input if its enable bit equals 0. n if the current instruction is extest, then the current state of each input pin is loaded. a bidirectional pin is treated as an input, regardless of the state of its enable. while in the shift-dr state, the bsr shift register is serially shifted toward the tdo pin. during the shift, bit 280 of the bsr is loaded from the tdi pin. the bsr output register is loaded with the contents of the bsr shift register in the update-dr state. if the current instruction is extest, the processors output pins, as well as those bidirectional pins that are enabled as outputs, are driven with their corresponding values from the bsr output register.
chapter 13 test and debug 257 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 50. boundary scan bit definitions 1 bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable 296 a6_e 263 a28_e 230 hit# 197 ap 164 rsvd 131 d40_e 295 a6 262 a28 229 a27_e 196 a20_e 163 rsvd 130 d40 294 vid1_e 2 261 ads_e 228 a27 195 a20 162 rsvd 129 d59_e 293 vid1 2 260 ads# 227 a4_e 194 breq_e 161 rsvd 128 d59 292 a22_e 259 a17_e 226 a4 193 breq 160 ahold 127 d9_e 291 a22 258 a17 225 a7_e 192 a11_e 159 inv 126 d9 290 pchk_e 257 a25_e 224 a7 191 a11 158 clk 125 d28_e 289 pch k# 256 a25 223 a8_e 190 a10_e 157 vid2_e 2 124 d28 288 a14_e 255 pw t_e 222 a8 189 a10 156 vid2 2 123 d56_e 287 a14 254 pwt 221 a15_e 188 apchk_e 155 cache_e 122 d56 286 a13_e 253 a12_e 220 a15 187 apchk# 154 cache# 121 d44_e 285 a13 252 a12 219 dc_e 186 smiact_e 153 mio_e 120 d44 284 a24_e 251 a9_e 218 d/c# 185 smiact# 152 m/io# 119 d11_e 283 a24 250 a9 217 a16_e 184 rsvd 151 ferr_e 118 d11 282 reset 249 a26_e 216 a16 183 a5_e 150 ferr# 117 dp3_e 281 a18_e 248 a26 215 a19_e 182 a5 149 d0_e 116 dp3 280 a18 247 a30_e 214 a19 181 intr 148 d0 115 d39_e 279 a21_e 246 a30 213 scyc_e 180 nm i 147 d1_e 114 d39 278 a21 245 vid0_e 2 212 scyc 179 init 146 d1 113 dp6_e 277 pcd_e 244 vid0 2 211 adsc_e 178 hold 145 d61_e 112 dp6 276 pcd 243 hitm_e 210 adsc# 177 ignne# 144 d61 111 d8_e 275 be4_e 242 hitm# 209 be6_e 176 smi# 143 d62_e 110 d8 274 be4# 241 a20m# 208 be6 175 wb/wt# 142 d62 109 d32_e 273 be7_e 240 flush# 207 be3_e 174 bf0 141 dp0_e 108 d32 272 be7# 239 a3_e 206 be3 173 boff# 140 dp0 107 d36_e 271 a23_e 238 a3 205 hlda_e 172 na# 139 d21_e 106 d36 270 a23 237 a31_e 204 hlda 171 bf1 138 d21 105 d51_e 269 lock_e 236 a31 203 be1_e 170 brdyc# 137 d57_e 104 d51 268 lock# 235 a29_e 202 be1# 169 brdy# 136 d57 103 d15_e 267 be0_e 234 a29 201 eads# 168 stpclk# 135 d5_e 102 d15 266 be0# 233 wr_e 200 be2_e 167 bf2 134 d5 101 d37_e 265 be5_e 232 w/r# 199 be2# 166 ken# 133 d24_e 100 d37 264 be5# 231 hit_e 198 ap_e 165 ewbe# 132 d24 99 d41_e
258 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information device identification register (dir). the dir is a 32-bit test data register selected during the execution of the idcode instruction. the fields of the dir and their values are shown in table 51 on page 259 and are defined as follows: n version code this 4-bit field is incremented by amd manufacturing for each major revision of silicon. n part number this 16-bit field identifies the specific processor model. n manufacturer this 11-bit field identifies the manufacturer of the component (amd). 98 d41 81 d49 64 d20_e 47 d35 30 d43_e 13 d45 97 d52_e 80 d17_e 63 d20 46 d10_e 29 d43 12 d60_e 96 d52 79 d17 62 d13_e 45 d10 28 d58_e 11 d60 95 d14_e 78 d19_e 61 d13 44 d53_e 27 d58 10 d22_e 94 d14 77 d19 60 dp5_e 43 d53 26 d26_e 9 d22 93 d29_e 76 d48_e 59 dp5 42 d34_e 25 d26 8 d63_e 92 d29 75 d48 58 d31_e 41 d34 24 d3_e 7 d63 91 d33_e 74 d47_e 57 d31 40 vid4_e 2 23 d3 6 dp7_e 90 d33 73 d47 56 d27_e 39 vid4 2 22 d55_e 5 dp7 89 rsvd 72 d16_e 55 d27 38 d7_e 21 d55 4 d4_e 88 d18_e 71 d16 54 d12_e 37 d7 20 d42_e 3 d4 87 d18 70 dp1_e 53 d12 36 dp4_e 19 d42 2 d2_e 86 d23_e 69 dp1 52 d50_e 35 dp4 18 vid3_e 2 1d2 85 d23 68 d46_e 51 d50 34 d54_e 17 vid3 2 0 reserved 84 d25_e 67 d46 50 d38_e 33 d54 16 d6_e 83 d25 66 dp2_e 49 d38 32 d30_e 15 d6 82 d49_e 65 dp2 48 d35_e 31 d30 14 d45_e notes: 1. tdi is the input to bit 296, and tdo is driven from the output of bit 0. the entries listed as pin_e (where pin is an output or bidirectional signal) are the enable bits. 2. supported on low-power versions only. table 50. boundary scan bit definitions 1 (continued) bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable
chapter 13 test and debug 259 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information n lsb the least significant bit (lsb) of the dir is always set to 1, as specified by the ieee 1149.1 standard. bypass register (br). the br is a test data register consisting of a 1-bit shift register that provides the shortest path between tdi and tdo. when the processor is not involved in a test operation, the br can be selected by an instruction to allow the transfer of test data through the processor without having to serially scan the test data through the bsr. this functionality preserves the state of the bsr and significantly reduces test time. the br register is selected by the bypass and highz instructions as well as by any instructions not supported by the AMD-K6-IIIE+ processor. tap instructions the processor supports the three instructions required by the ieee 1149.1 standardextest, sample/preload, and bypassas well as two additional optional instructions idcode and highz. table 52 shows the complete set of tap instructions supported by the processor along with the 5-bit instruction register encoding and the register selected by each instruction. table 51. device identification register version code (bits 31C28) part number (bits 27C12) manufacturer (bits 11C1) lsb (bit 0) xh 05d0h 00000000001b 1b table 52. supported tap instructions instruction encoding register description extest 1 00000b bsr sample inputs and drive outputs sample / preload 00001b bsr sample inputs and outputs, then load the bsr idcode 00010b dir read dir highz 00011b br float outputs and bidirectional pins bypass 2 00100bC11110b br undefined instruction, execute the bypass instruction bypass 3 11111b br c onnect tdi to tdo to bypass the bsr notes: 1. following the execution of the extest instruction, the processor must be reset in order to return to normal, non-test operati on. 2. these instruction encodings are undefined on the amd-k6- iii e+ processor and default to the bypass instruction. 3. because the tdi input contains an internal pullup, the bypass instruction is executed if the tdi input is not connected or op en during an instruction scan operation. the bypass instruction does not affect the normal operational state of the processor.
260 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information extest instruction. when the extest instruction is executed, the processor loads the bsr shift register with the current state of the input and bidirectional pins in the capture-dr state and drives the output and bidirectional pins with the corresponding values from the bsr output register in the update-dr state. sample/preload instruction. the sample/preload instruction performs two functions. these functions are as follows: n during the capture-dr state, the processor loads the bsr shift register with the current state of every input, output, and bidirectional pin. n during the update-dr state, the bsr output register is loaded from the bsr shift register in preparation for the next extest instruction. the sample/preload instruction does not affect the normal operational state of the processor. bypass instruction. the bypass instruction selects the br register, which reduces the boundary-scan length through the processor from 297 to one (tdi to br to tdo). the bypass instruction does not affect the normal operational state of the processor. idcode instruction. the idcode instruction selects the dir register, allowing the device identification code to be shifted out of the processor. this instruction is loaded into the ir when the tap controller is reset. the idcode instruction does not affect the normal operational state of the processor. highz instruction. the highz instruction forces all output and bidirectional pins to be floated. during this instruction, the br is selected and the normal operational state of the processor is not affected. tap controller state machine the tap controller state diagram is shown in figure 90 on page 261. state transitions occur on the rising edge of tck. the logic 0 or 1 next to the states represents the value of the tms signal sampled by the processor on the rising edge of tck.
chapter 13 test and debug 261 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 90. tap state diagram test-logic-reset shift-dr pause-dr update-dr update-ir 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 run-test/idle exit2-ir exit1-ir pause-ir shift-ir select-dr-scan select-ir-scan capture-dr capture-ir exit1-dr exit2-dr ieee std 1149.1-1990, copyright ? 1990. ieee. all rights reserved
262 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the states of the tap controller are described as follows: test-logic-reset. this state represents the initial reset state of the tap controller and is entered when the processor samples reset asserted, when trst# is asynchronously asserted, and when tms is sampled high for five or more consecutive clocks. in addition, this state can be entered from the select-ir-scan state. the ir is initialized with the idcode instruction, and the processors normal operation is not affected in this state. capture-dr. during the sample/preload instruction, the processor loads the bsr shift register with the current state of every input, output, and bidirectional pin. during the extest instruction, the processor loads the bsr shift register with the current state of every input and bidirectional pin. capture-ir. when the tap controller enters the capture-ir state, the processor loads 01b into the two least significant bits of the ir shift register and loads 000b into the three most significant bits of the ir shift register. shift-dr. while in the shift-dr state, the selected tdr shift register is serially shifted toward the tdo pin. during the shift, the most significant bit of the tdr is loaded from the tdi pin. shift-ir. while in the shift-ir state, the ir shift register is serially shifted toward the tdo pin. during the shift, the most significant bit of the ir is loaded from the tdi pin. update-dr. during the sample/preload instruction, the bsr output register is loaded with the contents of the bsr shift register. during the extest instruction, the output pins, as well as those bidirectional pins defined as outputs, are driven with their corresponding values from the bsr output register. update-ir. in this state, the ir output register is loaded from the ir shift register, and the current instruction is defined by the ir output register.
chapter 13 test and debug 263 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information the following states have no effect on the normal or test operation of the processor other than as shown in figure 90 on page 261: n run-test/idlethis state is an idle state between scan operations. n select-dr-scanthis is the initial state of the test data register state transitions. n select-ir-scanthis is the initial state of the instruction register state transitions. n exit1-drthis state is entered to terminate the shifting process and enter the update-dr state. n exit1-irthis state is entered to terminate the shifting process and enter the update-ir state. n pause-drthis state is entered to temporarily stop the shifting process of a test data register. n pause-irthis state is entered to temporarily stop the shifting process of the instruction register. n exit2-drthis state is entered in order to either terminate the shifting process and enter the update-dr state or to resume shifting following the exit from the pause-dr state. n exit2-irthis state is entered in order to either terminate the shifting process and enter the update-ir state or to resume shifting following the exit from the pause-ir state. 13.4 cache inhibit the AMD-K6-IIIE+ processor provides a means for inhibiting the normal operation of its internal l1 and l2 caches while still supporting an external cache. this capability allows system designers to disable the l1 and l2 caches during the testing and debug of an l3 cache. if the cache inhibit bit (bit 3) of test register 12 (tr12) is set to 0, the processors l1 and l2 caches are enabled and operate as described in cache organization on page 205. if the cache inhibit bit is set to 1, the l1 and l2 caches are disabled and no new cache lines are allocated. even though new allocations do not occur, valid l1 and l2 cache lines remain valid and are read by the processor when a requested address hits a cache line. in addition, the processor continues to support inquire cycles
264 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information initiated by the system logic, including the execution of writeback cycles when a modified cache line is hit. while the l1 and l2 are inhibited, the processor continues to drive the pcd output signal appropriately, which system logic can use to control external l3 caching. in order to completely disable the l1 and l2 caches so that no valid lines exist in the cache, the cache inhibit bit must be set to 1 and the cache must be flushed in one of the following ways: n asserting the flush# input signal n executing the wbinvd instruction n executing the invd instruction (modified cache lines are not written back to memory) n using the page flush/invalidate register (pfir) (see page flush/invalidate register (pfir) on page 223) 13.5 l2 cache and tag array testing level-2 cache array access register (l2aar) the AMD-K6-IIIE+ processor provides the level-2 cache array access register (l2aar) that allows for direct access to the l2 cache and l2 tag arrays. the 256-kbyte l2 cache in the AMD-K6-IIIE+ is organized as shown in figure 91 on page 265: n four 64-kbyte ways n each way contains 1024 sets n each set contains four 64-byte sectors (one sector in each way) n each sector contains two 32-byte cache lines n each cache line contains four 8-byte octets n each octet contains an upper and lower dword (4 bytes) each line within a sector contains its own mesi state bits, and associated with each sector is a tag and lru (least recently used) information.
chapter 13 test and debug 265 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 91. l2 cache organization for amd-k6?- iii e+ processor figure 92 shows the l2 cache sector and line organization. if bit 5 of the address of a cache line equals 1, then this cache line is stored in line 1 of a sector. similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in line 0 of a sector. figure 92. l2 cache sector and line organization the l2aar register is msr c000_0089h. the operation that is performed on the l2 cache is a function of the instruction executedrdmsr or wrmsrand the contents of the edx register. the edx register specifies the location of the access, and whether the access is to the l2 cache data or tags (refer to figure 93 on page 266). bit 20 of edx (t/d) determines whether the access is to the l2 cache data or tag. table 53 on 1024 sets set 0 64 bytes way 2 line1/mesi line0/mesi tag/lru 64 bytes way 1 line1/mesi line0/mesi tag/lru 64 bytes way 0 line1/mesi line0/mesi tag/lru 64 bytes way 3 line1/mesi line0/mesi tag/lru set 1023 upper dword lower dword octet 0 line 1 octet 1 octet 2 octet 3 upper dword lower dword line 0 sector
266 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information page 266 describes the operation that is performed based on the instruction and the t/d bit. figure 93. l2 tag or data location for the amd-k6?- iii e+ processoredx when the l2aar is read or written, edx is left unchanged. this facilitates multiple accesses when testing the entire cache/tag array. l2 cache data reads if the l2 cache data is read (as opposed to reading the tag information), the result (dword) is placed in eax in the format reserved 0 set 21 31 20 19 17 16 5 15 18 way 4321 6 symbol description bit set selects the desired cache set 15-6 line selects line1 (1) or line0 (0) 5 octet selects one of four octets 4-3 dword selects upper (1) or lower (0) dword 2 l i n e octet d w o r d t / d symbol description bit t/d selects tag (1) or data (0) access 20 way selects desired cache way 17-16 table 53. tag versus data selector instruction t/d (edx[20]) operation rdmsr 0 read dword from l2 data array into eax. dword location is specified by edx. rdmsr 1 read tag, line state and lru information from l2 tag array into eax. location of tag is specified by edx. wrmsr 0 write dword to the l2 data array using data in eax. dword location is specified by edx. wrmsr 1 write tag, line state and lru information into l2 tag array from eax. location of tag is specified by edx.
chapter 13 test and debug 267 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information as illustrated in figure 94. similarly, if the l2 cache data is written, the write data is taken from eax. figure 94. l2 data - eax l2 tag reads if the l2 tag is read (as opposed to reading the cache data), the result is placed in eax in the format as illustrated in figure 95 on page 268. similarly, if the l2 tag is written, the write data is taken from eax. when accessing the l2 tag, the line, octet, and dword fields of the edx register are ignored. when writing to the l2 tag, special consideration must be given to the least significant bit of the tag field of the eax register eax[15]. the length of the l2 tag required to support the 256-kbyte l2 cache on the AMD-K6-IIIE+ processor is 16 bits, which corresponds to bits 31:16 of the eax register. however, the processor provides a total of 17 bits for storing the l2 tag that is, 16 bits for the tag (eax[31:16]), plus an additional bit for internal purposes (eax[15]). during normal operation, the processor ensures that this additional bit (bit 15) always corresponds to the set in which the tag resides. note that bits 15:6 of the address determine the set, in which case if bit 15 is equal to 0, it addresses sets 0 through 511, and if bit 15 is equal to 1, it addresses sets 512 through 1023. in order to set the full 17-bit l2 tag properly when using the l2aar register, eax[15] must likewise correspond to the set in which the tag is being writtenthat is, eax[15] must be equal to edx[15] (refer to figure 93 on page 266 and figure 95 on page 268). it is important to note that this special consideration is required if the processor will subsequently be expected to properly execute instructions or access data from the l2 cache following the setup of the l2 cache by means of the l2aar register. if the intent of using the l2aar register is solely to test or debug the l2 cache without the subsequent intent of executing instructions or accessing data from the l2 cache, then this consideration is not required. 0 31 data
268 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 95. l2 tag information for the amd-k6?- iii e+ processoreax lru (least recently used). for the 4-way set associative l2 cache, each way has a 2-bit lru field for each sector. values for the lru field are 00b, 01b, 10b, and 11b, where 00b indicates that the sector is most recently used, and 11b indicates that the sector is least recently used (see figure 96 on page 268). eax[7:6] indicate lru information for way 0, eax[5:4] for way 1, eax[3:2] for way 2, and eax[1:0] for way 3. figure 96. lru byte 13.6 debug the AMD-K6-IIIE+ processor implements the standard x86 debug functions, registers, and exceptions. in addition, the processor supports the i/o breakpoint debug extension. the c m d reserved 0 tag 15 31 14 12 10 9 7 8 11 lru line0st line1st symbol description bit tag tag data read or written 31-15 line1st line 1 state (m=11, e=10, s=01, i=00) 11-10 line0st line 0 state (m=11, e=10, s=01, i=00) 9-8 lru two bits of lru for each way 7-0 7654 32 1 0 way 2 lru values 00b most recently used 01b used more recent than 10b, but less recent than 00b 10b used more recent than 11b, but less recent than 01b 11b least recently used way 3 way 0 way 1
chapter 13 test and debug 269 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information debug feature assists programmers and system designers during software execution tracing by generating exceptions when one or more events occur during processor execution. the exception handler, or debugger, can be written to perform various tasks, such as displaying the conditions that caused the breakpoint to occur, displaying and modifying register or memory contents, or single-stepping through program execution. the following sections describe the debug registers and the various types of breakpoints and exceptions that the processor supports.
270 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information debug registers figures 97 through 100 show the 32-bit debug registers supported by the processor. figure 97. debug register dr7 9876543210 10 11 12 13 14 15 l 2 l 1 l 3 g 3 g e l e l 0 g 0 g 1 g 2 g d 25 24 23 22 21 20 19 18 17 16 26 27 28 29 30 31 r/w 3 len 3 r/w 2 len 2 r/w 1 len 1 r/w 0 len 0 reserved symbol description bits len 3 length of breakpoint #3 31C30 r/w 3 type of transaction(s) to trap 29C28 len 2 length of breakpoint #2 27C26 r/w 2 type of transaction(s) to trap 25C24 len 1 length of breakpoint #1 23C22 r/w 1 type of transaction(s) to trap 21C20 len 0 length of breakpoint #0 19C18 r/w 0 type of transaction(s) to trap 17C16 symbol description bit gd general detect enabled 13 ge global exact breakpoint enabled 9 le local exact breakpoint enabled 8 g3 global exact breakpoint # 3 enabled 7 l3 local exact breakpoint # 3 enabled 6 g2 global exact breakpoint # 2 enabled 5 l2 local exact breakpoint # 2 enabled 4 g1 global exact breakpoint # 1 enabled 3 l1 local exact breakpoint # 1 enabled 2 g0 global exact breakpoint # 0 enabled 1 l0 local exact breakpoint # 0 enabled 0
chapter 13 test and debug 271 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 98. debug register dr6 figure 99. debug registers dr5 and dr4 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 b 1 b 2 b s b 0 b t b d b 3 reserved symbol description bit bt breakpoint task switch 15 bs breakpoint single step 14 bd breakpoint debug access detected 13 b3 breakpoint #3 condition detected 3 b2 breakpoint #2 condition detected 2 b1 breakpoint #1 condition detected 1 b0 breakpoint #0 condition detected 0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr5 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr4
272 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 100. debug registers dr3, dr2, dr1, and dr0 dr3Cdr0. the processor allows the setting of up to four breakpoints. dr3Cdr0 contain the linear addresses for breakpoint 3 through breakpoint 0, respectively, and are compared to the linear addresses of processor cycles to determine if a breakpoint occurs. debug register dr7 defines the specific type of cycle that must occur in order for the breakpoint to occur. dr5Cdr4. when debugging extensions are disabled (bit 3 of cr4 is set to 0), the dr5 and dr4 registers are mapped to dr7 and dr6, respectively, in order to be software compatible with previous generations of x86 processors. when debugging 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 3 32-bit linear address dr3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 0 32-bit linear address dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 2 32-bit linear address dr2 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 1 32-bit linear address dr1
chapter 13 test and debug 273 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information extensions are enabled (bit 3 of cr4 is set to 1), any attempt to load dr5 or dr4 results in an undefined opcode exception. likewise, any attempt to store dr5 or dr4 also results in an undefined opcode exception. dr6. if a breakpoint is enabled in dr7, and the breakpoint conditions as defined in dr7 occur, then the corresponding b bit (b3Cb0) in dr6 is set to 1. in addition, any other breakpoints defined using these particular breakpoint conditions are reported by the processor by setting the appropriate b-bits in dr6, regardless of whether these breakpoints are enabled or disabled. however, if a breakpoint is not enabled, a debug exception does not occur for that breakpoint. if the processor decodes an instruction that writes or reads dr7 through dr0, the bd bit (bit 13) in dr6 is set to 1 (if enabled in dr7) and the processor generates a debug exception. this operation allows control to pass to the debugger prior to debug register access by software. if the trap flag (bit 8) of the eflags register is set to 1, the processor generates a debug exception after the successful execution of every instruction (single-step operation) and sets the bs bit (bit 14) in dr6 to indicate the source of the exception. when the processor switches to a new task and the debug trap bit (t bit) in the corresponding task state segment (tss) is set to 1, the processor sets the bt bit (bit 15) in dr6 and generates a debug exception. dr7. when set to 1, l3Cl0 locally enable breakpoints 3 through 0, respectively. l3Cl0 are set to 0 whenever the processor executes a task switch. setting l3Cl0 to 0 disables the breakpoints and ensures that these particular debug exceptions are only generated for a specific task. when set to 1, g3Cg0 globally enable breakpoints 3 through 0, respectively. unlike l3Cl0, g3Cg0 are not set to 0 whenever the processor executes a task switch. not setting g3Cg0 to 0 allows breakpoints to remain enabled across all tasks. if a breakpoint is enabled globally but disabled locally, the global enable overrides the local enable.
274 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the le (bit 8) and ge (bit 9) bits in dr7 have no effect on the operation of the processor and are provided in order to be software-compatible with previous generations of x86 processors. when set to 1, the gd bit in dr7 (bit 13) enables the debug exception associated with the bd bit (bit 13) in dr6. this bit is set to 0 when a debug exception is generated. len3Clen0 and rw3Crw0 are two-bit fields in dr7 that specify the length and type of each breakpoint as defined in table 54. debug exceptions a debug exception is categorized as either a debug trap or a debug fault. n a debug trap calls the debugger following the execution of the instruction that caused the trap. n a debug fault calls the debugger prior to the execution of the instruction that caused the fault. all debug traps and faults generate either an interrupt 01h or an interrupt 03h exception. table 54. dr7 len and rw definitions len bits 1 notes: 1. len bits equal to 10b is undefined. rw bits breakpoint 00b 00b 2 2. when rw equals 00b, len must be equal to 00b. instruction execution 00b 01b one-byte data write 01b two-byte data write 11b four-byte data write 00b 10b 3 3. when rw equals 10b, debugging extensions (de) must be enabled (bit 3 of cr4 must be set to 1). if de is set to 0, then rw equal to 10b is undefined. one-byte i/o read or write 01b two-byte i/o read or write 11b four-byte i/o read or write 00b 11b one-byte data read or write 01b two-byte data read or write 11b four-byte data read or write
chapter 13 test and debug 275 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information interrupt 01h. the following events are considered debug traps that cause the processor to generate an interrupt 01h exception: n enabled breakpoints for data and i/o cycles n single step trap n ta sk sw itch trap the following events are considered debug faults that cause the processor to generate an interrupt 01h exception: n enabled breakpoints for instruction execution n bd bit in dr6 set to 1 interrupt 03h. the int 3 instruction is defined in the x86 architecture as a breakpoint instruction. this instruction causes the processor to generate an interrupt 03h exception. this exception is a debug trap because the debugger is called following the execution of the int 3 instruction. the int 3 instruction is a one-byte instruction (opcode cch) typically used to insert a breakpoint in software by writing cch to the address of the first byte of the instruction to be trapped (the target instruction). following the trap, if the target instruction is to be executed, the debugger must replace the int 3 instruction with the first byte of the target instruction.
276 test and debug chapter 13 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 14 clock control 277 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 14 clock control 14.1 clock control states the standard-power versions of the AMD-K6-IIIE+ processor support five modes of clock control. the low-power versions of the AMD-K6-IIIE+ processor support six modes of clock control. the processor can transition between these modes to maximize performance, to minimize power dissipation, or to provide a balance between performance and power. (see power dissipation on page 291 for the maximum power dissipation of the AMD-K6-IIIE+ processor within the normal and reduced-power states.) the clock-control states supported are: n normal state the processor is running in real mode, virtual-8086 mode, protected mode, or system management mode (smm). in this state, all clocks are runningincluding the external bus clock clk and the internal processor clockand the full features and functions of the processor are available. n halt state this low-power state is entered following the successful execution of the hlt instruction. during this state, the internal processor clock is stopped. n stop grant state this low-power state is entered following the recognition of the assertion of the stpclk# signal. during this state, the internal processor clock is stopped. n stop grant inquire state this state is entered from the halt state and the stop grant state as the result of a system-initiated inquire cycle. n enhanced power management (epm) stop grant state : this low-power state is available on low--power versions of the processor. it is entered following the write of a non-zero value to the sgtc field of the epm 16-byte i/o block for the purpose of performing dynamic processor core frequency and voltage id state transitions using amd powernow! technology. during this state, the internal processor clock is stopped. n stop clock state this low-power state is entered from the stop grant state when the clk signal is stopped.
278 clock control chapter 14 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 101 and figure 102 illustrate the clock control state transitions on the standard-power and low-power versions, respectively, of the AMD-K6-IIIE+ processor. each of the reduced-power states are described in the following sections. figure 101. clock control state transitions for standard-power versions of the amd-k6?- iii e+ processor eads# asserted eads# asserted hlt instruction stop grant state normal mode - real - virtual-8086 - protected - smm halt state stop clock state reset, smi#, init, or intr asserted stop grant inquire state stpclk# asserted stpclk# negated, or reset asserted clk started clk stopped writeback completed writeback completed
chapter 14 clock control 279 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 102. clock control state transitions for low-power versions of the amd-k6?- iii e+ processor clk started clk stopped sgtc timer expires non-zero value written to sgtc eads# asserted eads# asserted hlt instruction stop grant state normal mode C real C virtual-8086 C protected C smm halt state stop clock state reset, smi#, init, or intr asserted stop grant inquire state stpclk# asserted stpclk# negated, or reset asserted clk started clk stopped writeback completed writeback completed epm stop grant state
280 clock control chapter 14 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 14.2 halt state enter halt state during the execution of the hlt instruction, the AMD-K6-IIIE+ processor executes a halt special cycle. after brdy# is sampled asserted during this cycle, and then ewbe# is also sampled asserted (if not masked off), the processor enters the halt state in which the processor disables most of its internal clock distribution. in order to support the following operations, the internal phase-lock loop (pll) still runs, and some internal resources are still clocked in the halt state: n inquire cyclesthe processor continues to sample ahold, boff#, and hold in order to support inquire cycles that are initiated by the system logic. the processor transitions to the stop grant inquire state during the inquire cycle. after returning to the halt state following the inquire cycle, the processor does not execute another halt special cycle. n flush cyclesthe processor continues to sample flush#. if flush# is sampled asserted, the processor performs the flush operation in the same manner as it is performed in the normal state. upon completing the flush operation, the processor executes the halt special cycle, which indicates the processor is in the halt state. n time stamp counter (tsc)the tsc continues to count in the halt state. n signal samplingthe processor continues to sample init, intr, nmi, reset, and smi#. after entering the halt state, all signals driven by the processor retain their state as they existed following the completion of the halt special cycle. exit halt state the AMD-K6-IIIE+ processor remains in the halt state until it samples init, intr (if interrupts are enabled), nmi, reset, or smi# asserted. if any of these signals is sampled asserted, the processor returns to the normal state and performs the corresponding operation. all of the normal requirements for recognition of these input signals apply within the halt state. 14.3 stop grant state enter stop grant state after recognizing the assertion of stpclk#, the AMD-K6-IIIE+ processor flushes its instruction pipelines, completes all pending and in-progress bus cycles, and acknowledges the
chapter 14 clock control 281 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information stpclk# assertion by executing a stop grant special bus cycle. after brdy# is sampled asserted during this cycle, and then ewbe# is also sampled asserted (if not masked off), the processor enters the stop grant state. the stop grant state is like the halt state in that the processor disables most of its internal clock distribution in the stop grant state. in order to support the following operations, the internal pll still runs, and some internal resources are still clocked in the stop grant state: n inquire cyclesthe processor transitions to the stop grant inquire state during an inquire cycle. after returning to the stop grant state following the inquire cycle, the processor does not execute another stop grant special cycle. n time stamp counter (tsc)the tsc continues to count in the stop grant state. n signal samplingthe processor continues to sample init, intr, nmi, reset, and smi#. flush# is not recognized in the stop grant state (unlike while in the halt state). upon entering the stop grant state, all signals driven by the processor retain their state as they existed following the completion of the stop grant special cycle. exit stop grant state the AMD-K6-IIIE+ processor remains in the stop grant state until it samples stpclk# negated or reset asserted. if stpclk# is sampled negated, the processor returns to the normal state in less than 10 bus clock (clk) periods. after the transition to the normal state, the processor resumes execution at the instruction boundary on which stpclk# was initially recognized. if stpclk# is recognized as negated in the stop grant state and subsequently sampled asserted prior to returning to the normal state, the AMD-K6-IIIE+ processor guarantees that a minimum of one instruction is executed prior to re-entering the stop grant state. if init, intr (if interrupts are enabled), flush#, nmi, or smi# are sampled asserted in the stop grant state, the
282 clock control chapter 14 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information processor latches the edge-sensitive signals (init, flush#, nmi, and smi#), but otherwise does not exit the stop grant state to service the interrupt. when the processor returns to the normal state due to sampling stpclk# negated, any pending interrupts are recognized after returning to the normal state. to ensure their recognition, all of the normal requirements for these input signals apply within the stop grant state. if reset is sampled asserted in the stop grant state, the processor immediately returns to the normal state and the reset process begins. 14.4 stop grant inquire state enter stop grant inquire state the stop grant inquire state is entered from the stop grant state or the halt state when eads# is sampled asserted during an inquire cycle initiated by the system logic. the AMD-K6-IIIE+ processor responds to an inquire cycle in the same manner as in the normal state by driving hit# and hitm#. if the inquire cycle hits a modified cache line, the processor performs a writeback cycle. exit stop grant inquire state following the completion of any writeback, the processor returns to the state from which it entered the stop grant inquire state.
chapter 14 clock control 283 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 14.5 epm stop grant state enter epm stop grant state this state is supported on the low-power versions of the AMD-K6-IIIE+ processor. after receiving a write of a non-zero value to the sgtc (stop grant time-out counter) field located within the epm 16-byte i/o block, the processor flushes its instruction pipelines, completes all pending and in-progress bus cycles, and performs the following: n drives the processor vid[4:0] output pins to the value stored in the vido field of the epm 16-byte i/o block (see epm 16-byte i/o block on page 146) if the vidc bit is set to 1. n forwards the processor-to-bus clock ratio stored in the ibf[2:0] field of the epm 16-byte i/o block to the internal pll if the bdc[1:0] value is set to 1xb. the epm stop grant state is like the halt state in that the processor disables most of its internal clock distribution in the epm stop grant state. in order to support the following operations, the internal pll still runs, and some internal resources are still clocked in the epm stop grant state. n time stamp counter (tsc): the tsc continues to count in the epm stop grant state. n signal sampling: the processor continues to sample init, intr, nmi, reset, and smi#. unlike the halt and stop grant states, system-initiated inquire cycles are not supported and must be prevented during the epm stop grant state. flush# is not recognized in the epm stop grant state (unlike while in the halt state). upon entering the epm stop grant state, all signals driven by the processor retain their state as they existed following the completion of the epm stop grant special cycle. exit epm stop grant state the processor remains in the epm stop grant state until the allotted time expires, as determined by the value written to the sgtc field, or until reset is sampled asserted. once the allotted time expires, the processor returns to the normal state. after the transition to the normal state, the processor resumes execution at the instruction boundary on which the epm stop grant state was entered.
284 clock control chapter 14 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information if init, intr (if interrupts are enabled), flush#, nmi, or smi# are sampled asserted in the epm stop grant state, the processor latches the edge-sensitive signals (init, flush#, nmi, and smi#), but otherwise does not exit the epm stop grant state to service the interrupt. when the processor returns to the normal state, any pending interrupts are recognized. to ensure their recognition, all of the normal requirements for these input signals apply within the epm stop grant state. if reset is sampled asserted in the epm stop grant state, the processor immediately returns to the normal state and the reset process begins.
chapter 14 clock control 285 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 14.6 stop clock state enter stop clock state if the clk signal is stopped while the AMD-K6-IIIE+ processor is in the stop grant state, the processor enters the stop clock state. because all internal clocks and the pll are not running in the stop clock state, the stop clock state represents the minimum-power state of all clock control states. the clk signal must be held low while it is stopped. the stop clock state cannot be entered from the halt state. intr is the only input signal that is allowed to change states while the processor is in the stop clock state. however, intr is not sampled until the processor returns to the stop grant state. all other input signals must remain unchanged in the stop clock state. exit stop clock state the AMD-K6-IIIE+ processor returns to the stop grant state from the stop clock state after the clk signal is started and the internal pll has stabilized. pll stabilization is achieved after the clk signal has been running within its specification for a minimum of 1.0 ms. the frequency of clk when exiting the stop clock state can be different than the frequency of clk when entering the stop clock state. the state of the bf[2:0] signals when exiting the stop clock state is ignored because the bf[2:0] signals are only sampled during the falling transition of reset.
286 clock control chapter 14 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 15 electrical data 287 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 15 electrical data this chapter includes specifications for the operating ranges, absolute ratings, and dc characteristics of the AMD-K6-IIIE+ embedded processor. nominal and maximum power dissipation values for the AMD-K6-IIIE+ processor during normal and reduced power states are listed. the chapter concludes with a discussion of power and grounding requirements.
288 electrical data chapter 15 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 15.1 operating ranges the AMD-K6-IIIE+ processor is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in table 55 and table 56. table 55. operating ranges for low-power amd-k6?- iii e+ devices parameter parameter description 400 mhz 450 mhz 500 mhz v cc2 1 notes: 1. v cc2 and v cc3 are referenced from v ss . core supply voltage (minimum) 1.5 v 2 2. v cc2 specification for 1.6-v component. 1.6 v 3 3. v cc2 specification for 1.7-v component. 1.7 v 4 4. v cc2 specification for 1.8-v component. v cc2 1 core supply voltage (nominal) 1.6 v 2 1.7 v 3 1.8 v 4 v cc2 1 core supply voltage (maximum) 1.7 v 2 1.8 v 3 1.9 v 4 v cc3 1 i/o supply voltage (minimum) 3.135 v v cc3 1 i/o supply voltage (nominal) 3.30 v v cc3 1 i/o supply voltage (maximum) 3.6 v t case case temperature (minimum) 5 5. case temperature range required for amd-k6- iiie+/400xtz, AMD-K6-IIIE+/450xpz, and amd-k6- iiie+/500xnz valid ordering part number combinations, where x represents the package type. see table 79 on page 336 for a complete list of valid opns. 0 ? c t case case temperature (maximum) 5 85 ? c table 56. operating ranges for standard-power amd-k6?- iii e+ devices parameter parameter description 400 mhz 450 mhz 500 mhz 550 mhz v cc2 1 notes: 1. v cc2 and v cc3 are referenced from v ss . core supply voltage (minimum) 2 2. v cc2 specification for 2.0-v component. 1.9 v v cc2 1 core supply voltage (nominal) 2 2.0 v v cc2 1 core supply voltage (maximum) 2 2.1 v v cc3 1 i/o supply voltage (minimum) 3.135 v v cc3 1 i/o supply voltage (nominal) 3.30 v v cc3 1 i/o supply voltage (maximum) 3.6 v t case case temperature (minimum) 3 3. case temperature range required for amd-k6- iiie+/xxxyacr valid ordering part number combi nations, where xxx represents the pro- cessor core frequency and y represents the package type, as defined in table 79 on page 336. 0 ? c t case case temperature (maximum) 3 70 ? c
chapter 15 electrical data 289 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 15.2 absolute ratings the AMD-K6-IIIE+ processor is not designed to be operated beyond the operating ranges listed in table 55 and table 56. exposure to conditions outside these operating ranges for extended periods of time can affect long-term reliability. permanent damage can occur if the absolute ratings listed in table 57 are exceeded. 15.3 dc characteristics the dc characteristics of the amd-k6?-iiie+ processor are shown in table 58. table 57. absolute ratings parameter description minimum maximum v cc2 core supply voltage C0.5 v 2.2 v v cc3 i/o supply voltage C0.5 v 3.6 v v pin 1 notes: 1. v pin (the voltage on any i/o pin) must not be greater than 0.4 v above the voltage being applied to v cc3 . in addition, the v pin voltage must never exceed 3.8 v. voltage on any i/o pin C0.5 v v cc3 + 0.4 v and ? 3.8 v t case (under bias) case temperature C65 ? c +110 ? c t storage storage temperature C65 ? c+150 ? c table 58. dc characteristic s for the amd-k6?- iii e+ processor symbol parameter description preliminary data comments min max v il input low voltage C0.3 v +0.8 v v ih 1 input high voltage 2.0 v vcc3+0.3 v v ol output low voltage 0.4 v i ol = 4.0-ma load v oh output high voltage 2.4 v i oh = 3.0-ma load
290 electrical data chapter 15 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information i cc2 low power 1.6-v power supply current 6.15 a 400 mhz 2,3,4 1.7-v power supply current 7.60 a 450 mhz 2,3 1.8-v power supply current 8.60 a 500 mhz 2,3 i cc2 standard power 2.0 v power supply current 8.70 a 400 mhz 3,4,5 9.25 a 450 mhz 3,5 9.75 a 500 mhz 3,5 10.30 a 550 mhz 3,5 i cc3 standard and low power 3.3 v power supply current 0.65 a 400 mhz 3,4,6 0.66 a 450 mhz 3,6 0.68 a 500 mhz 3,6 0.69 a 550 mhz 3,6 i li 7 input leakage current ? 15 m a i lo 7 output leakage current ? 15 m a i il 8 input leakage current bias with pullup C500 m a i ih 9 input leakage current bias with pulldown 500 m a c in input capacitance 10 pf c out output capacitance 15 pf c out i/o capacitance 20 pf c clk clk capacitance 10 pf c tin test input capacitance (tdi, tms, trst#) 10 pf c tout test output capacitance (tdo) 15 pf c tck tck capacitance 10 pf notes: 1. v cc3 refers to the voltage being applied to v cc3 during functional operation. 2. v cc2 = maximum v cc2 as listed in table 55 on page 288 the maximum power supply current must be taken into account when designing a power supply. 3. this specification applies to components using a clk frequency of 100 mhz. 4. this specification applies to components using a clk frequency of 66 mhz (66-mhz bus applies to 400-mhz part only). 5. v cc2 = 2.1 v the maximum power supply current must be taken into account when designing a power supply. 6. v cc3 = 3.6 vthe maximum power supply current must be taken into account when designing a power supply. 7. refers to inputs and i/o without an internal pullup resistor and 0 ? v in ? v cc3. 8. refers to inputs with an internal pullup and v il = 0.4 v. 9. refers to inputs with an internal pulldown and v ih = 2.4 v. table 58. dc characteristic s for the amd-k6?- iii e+ processor (continued) symbol parameter description preliminary data comments min max
chapter 15 electrical data 291 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 15.4 power dissipation table 59 and table 60 contain the application power dissipation of the low-power and standard-power AMD-K6-IIIE+ processor during normal and reduced power states. table 61 on page 292 shows the supported voltages and operating frequencies for low-power versions of AMD-K6-IIIE+ processors enabled with amd powernow! technology. table 59. p ower dissipation for low-power amd-k6?- iii e+ devices power dissipation 400 mhz 1,2 notes: 1. this specification applies to components using a clk frequency of 100 mhz. 2. this specification applies to components using a clk frequency of 66 mhz. 450 mhz 1 500 mhz 1 application power active 3 3. the active application power measurements were taken by running a suite of embedded benchmarks covering four major embedded market segments: automotive, office automation, networking, and telecommunications. 7.10 w 8.95 w 11.40 w amd powernow! technology power saving mode 4 4. amd powernow! technology power saving mode represents averaged values measured while running the processor in the lowest settings supported by amd powernow! technology. 2.95 w thermal design power (maximum) 5,6 5. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for therm al dissipation for the amd-k6-2e+ processor. 6. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with v cc2 = nominal v cc2 as listed in table 55 on page 288 and v cc3 = 3.3 v. 9.50 w 12.00 w 14.50 w stop grant/halt (maximum) 6,7 7. the clk signal and the internal pll are still running, but most internal clocking has stopped. v cc nominal 2.50 w stop clock (maximum) 6,8 8. the clk signal, the internal pll, and all internal clocking has stopped. v cc nominal 1.60 w 1.90 w lowest operating v cc 9 9. the lowest operating v cc is 1.4 v. 1.30 w
292 electrical data chapter 15 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 60. p ower dissipation for standard-power amd-k6?- iii e+ devices power dissipation 400 mhz 1,2 notes: 1. this specification applies to components using a clk frequency of 100 mhz. 2. this specification applies to components using a clk frequency of 66 mhz. 450 mhz 1 500 mhz 1 550 mhz 1 application power active 3 3. the active application power measurements were taken by running a suite of embedded benchmarks covering four major embedded market segments: automotive, office automation, networking, and telecommunications. 11.75 w 13.00 w 14.35 w 15.70 w thermal design power (maximum) 4,5 4. the maximum power dissipated in the normal clock control state must be taken into account when designing a solution for therm al dissipation for the amd-k6-2e+ processor. 5. maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with v cc2 = 2.0 v and v cc3 = 3.3 v. 16.50 w 17.50 w 18.50 w 19.50 w stop grant/halt (maximum) 5,6 6. the clk signal and the internal pll are still running, but most internal clocking has stopped. 4.50 w stop clock (maximum) 5,7 7. the clk signal, the internal pll, and all internal clocking has stopped. 4.00 w table 61. supported frequencies and voltages for low-power amd-k6?- iii e+ processors enabled with amd powernow!? technology ordering part number 1 notes: 1. an x in this column represents the package type. see table 79, amd-k6?-iiie+ embedded processor valid ordering part number com- binations, on page 336. core voltage range of supported operating frequencies 2 2. amd powernow! technology enables the operating frequency to step down in increments corresponding to the available bus freque ncy multipliers. note that 250-mhz operation is not supported due to exclusion of 2.5 bus frequency multiplier. active power 3 3. active application power dissipation for highest and lowest supported frequency at specified voltage. amd-k6- iii e+500anz 1.8 v 500C200 mhz 11.40C5.80 w 1.7 v 450C200 mhz 8.95C4.90 w 1.6 v 400C200 mhz 7.10C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w amd-k6- iii e+450apz 1.7 v 450C200 mhz 8.95C4.90 w 1.6 v 400C200 mhz 7.10C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w amd-k6- iii e+400xtz 1.6 v 400C200 mhz 7.10C4.20 w 1.5 v 350C200 mhz 5.60C3.70 w 1.4 v 300C200 mhz 4.30C2.95 w
chapter 15 electrical data 293 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 15.5 power and grounding power connections the AMD-K6-IIIE+ processor is a dual voltage device. two separate supply voltages are required: v cc2 and v cc3 . n v cc2 provides the core voltage for the processor. n v cc3 provides the i/o voltage. see operating ranges on page 288 for the value and range of v cc2 and v cc3 . the power and ground pins for each package are listed in table 76 on page 327 and table 78 on page 331. table 74 on page 323 lists the pin differences between the two packages. the large number of power and ground pins are provided to ensure that the processor and package maintain a clean and stable power distribution network. for proper operation and functionality, all v cc2 , v cc3 , and v ss pins must be connected to the appropriate planes in the circuit board. the power planes have been arranged in a pattern to simplify routing and minimize crosstalk on the circuit board. the isolation region between two voltage planes must be at least 0.254mm if they are in the same layer of the circuit board. (see figure 103 on page 294.) in order to maintain a low-impedance current sink and reference, the ground plane must never be split. although the AMD-K6-IIIE+ processor has two separate supply voltages, there are no special power sequencing requirements. the best procedure is to minimize the time between which v cc2 and v cc3 are either both on or both off.
294 electrical data chapter 15 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 103. suggested component placement for cpga package decoupling recommendations in addition to the isolation region mentioned in power connections on page 293, adequate decoupling capacitance is required between the two system power planes and the ground plane to minimize ringing and to provide a low-impedance path for return currents. suggested decoupling capacitor placement is shown in figure 103. surface-mounted capacitors should be used under the processors zif socket to minimize resistance and inductance in the lead lengths while maintaining minimal height. for information and recommendations about the specific value, quantity, and location of the capacitors, see the amd-k6 ? processor power supply design application note , order# 21103. 0.254mm (min.) for isolation region v cc2 (core) plane v cc3 (i/o) plane c1 cc5 cc3 c2 + + + + c5 c6 c7 c11 c12 c13 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 c28 c29 c30 c31 cc4 + cc6 cc10 cc1 cc2 cc9 cc8 cc7 c8 c9 c10 c14 c15 c16
chapter 15 electrical data 295 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information pin connection requirements for proper operation, the following requirements for signal pin connections must be met: n do not drive address and data signals into large capacitive loads at high frequencies. if necessary, use buffer chips to drive large capacitive loads. n leave all nc (no-connect) pins unconnected. n unused inputs should always be connected to an appropriate signal level. ? active low inputs that are not being used should be connected to v cc3 through a 20-k w pullup resistor. ? active high inputs that are not being used should be connected to gnd through a pulldown resistor. n reserved signals can be treated in one of the following ways: ? as no-connect (nc) pins, in which case these pins are left unconnected ? as pins connected to the system logic as defined by the industry-standard super7 and socket 7 interface ? any combination of nc and socket 7 pins n keep trace lengths to a minimum.
296 electrical data chapter 15 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 16 signal switching characteristics 297 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 16 signal switching characteristics the AMD-K6-IIIE+ processor signal switching characteristics are presented in table 62 through table 71 on the following pages. valid delay, float, setup, and hold timing specifications are listed. these specifications are provided for the system designer to determine if the timings necessary for the processor to interface with the system logic are met. n table 62 on page 298 and table 63 on page 299 contain the switching characteristics of the clk input. n table 64 on page 300 through table 67 on page 306 contain the timings for the normal operation signals. n table 68 on page 308 and table 69 on page 309 contain the timings for reset and the configuration signals. n table 70 on page 310 and table 71 on page 310 contain the timings for the test operation signals. all signal timings provided are: n measured between clk, tck, or reset at 1.5 v and the corresponding signal at 1.5 vthis applies to input and output signals that are switching from low to high, or from high to low n based on input signals applied at a slew rate of 1 v/ns between 0 v and 3 v (rising) and 3 v to 0 v (falling) n valid within the operating ranges given in operating ranges on page 288 n based on a load capacitance (c l ) of 0 pf
298 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 16.1 clk switching characteristics table 62 and table 63 on page 299 contain the switching characteristics of the clk input to the AMD-K6-IIIE+ processor for 100-mhz and 66-mhz bus operation, respectively, as measured at the voltage levels indicated by figure 104 on page 299. the clk period stability parameter specifies the variance (jitter) allowed between successive periods of the clk input measured at 1.5 v. this parameter must be considered as one of the elements of clock skew between the AMD-K6-IIIE+ processor and the system logic. 16.2 clock switching characteristics for 100-mhz bus operation table 62. clk switching characteristics for 100-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 33.3 mhz 100 mhz in normal mode t 1 clk period 10.0 ns 104 in normal mode t 2 clk high time 3.0 ns 104 t 3 clk low time 3.0 ns 104 t 4 clk fall time 0.15 ns 1.5 ns 104 t 5 clk rise time 0.15 ns 1.5 ns 104 clk period stability 1 notes: 1. the jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz. ? 250 ps
chapter 16 signal switching characteristics 299 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 16.3 clock switching characteristics for 66-mhz bus operation figure 104. clk waveform table 63. clk switching characteristics for 66-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 33.3 mhz 66.6 mhz in normal mode t 1 clk period 15.0 ns 30.0 ns 104 in normal mode t 2 clk high time 4.0 ns 104 t 3 clk low time 4.0 ns 104 t 4 clk fall time 0.15 ns 1.5 ns 104 t 5 clk rise time 0.15 ns 1.5 ns 104 clk period stability 1 notes: 1. the jitter frequency power spectrum peaking must occur at frequencies greater than (frequency of clk)/3 or less than 500 khz. ? 250 ps t 5 2.0 v 1.5 v 0.8 v t 2 t 3 t 4 t 1
300 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 16.4 valid delay, float, setup, and hold timings valid delay and float timing the maximum valid delay timings are provided to allow a system designer to determine if setup times to the system logic can be met. likewise, the minimum valid delay timings are used to analyze hold times to the system logic. n valid delay and float timings are given for output signals during functional operation and are given relative to the rising edge of clk. n during boundary-scan testing, valid delay and float timings for output signals are with respect to the falling edge of tck. setup and hold timing the setup and hold time requirements for the AMD-K6-IIIE+ processor input signals must be met by the system logic to assure the proper operation of the AMD-K6-IIIE+ processor. n the setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of clk and tck, respectively. 16.5 output delay timings for 100-mhz bus operation table 64. output delay timings for 100-mhz bus operation symbol parameter description preliminary data figure min max t 6 a[31:3] valid delay 1.1 ns 4.0 ns 106 t 7 a[31:3] float delay 7.0 ns 107 t 8 ads# valid delay 1.0 ns 4.0 ns 106 t 9 ads# float delay 7.0 ns 107 t 10 adsc# valid delay 1.0 ns 4.0 ns 106 t 11 adsc# float delay 7.0 ns 107 t 12 ap valid delay 1.0 ns 5.5 ns 106 t 13 ap float delay 7.0 ns 107 t 14 apchk# valid delay 1.0 ns 4.5 ns 106 t 15 be[7:0]# valid delay 1.0 ns 4.0 ns 106 t 16 be[7:0]# float delay 7.0 ns 107 t 17 breq valid delay 1.0 ns 4.0 ns 106 t 18 cache# valid delay 1.0 ns 4.0 ns 106
chapter 16 signal switching characteristics 301 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information t 19 cache# float delay 7.0 ns 107 t 20 d/c# valid delay 1.0 ns 4.0 ns 106 t 21 d/c# float delay 7.0 ns 107 t 22 d[63:0] write data valid delay 1.3 ns 4.5 ns 106 t 23 d[63:0] write data float delay 7.0 ns 107 t 24 dp[7:0] write data valid delay 1.3 ns 4.5 ns 106 t 25 dp[7:0] write data float delay 7.0 ns 107 t 26 ferr# valid delay 1.0 ns 4.5 ns 106 t 27 hit# valid delay 1.0 ns 4.0 ns 106 t 28 hitm# valid delay 1.1 ns 4.0 ns 106 t 29 hlda valid delay 1.0 ns 4.0 ns 106 t 30 lock# valid delay 1.1 ns 4.0 ns 106 t 31 lock# float delay 7.0 ns 107 t 32 m/io# valid delay 1.0 ns 4.0 ns 106 t 33 m/io# float delay 7.0 ns 107 t 34 pcd valid delay 1.0 ns 4.0 ns 106 t 35 pcd float delay 7.0 ns 107 t 36 pchk# valid delay 1.0 ns 4.5 ns 106 t 37 pwt valid delay 1.0 ns 4.0 ns 106 t 38 pwt float delay 7.0 ns 107 t 39 scyc valid delay 1.0 ns 4.0 ns 106 t 40 scyc float delay 7.0 ns 107 t 41 smiact# valid delay 1.0 ns 4.0 ns 106 t 42 w/r# valid delay 1.0 ns 4.0 ns 106 t 43 w/r# float delay 7.0 ns 107 table 64. output delay timings for 100-mhz bus operation (continued) symbol parameter description preliminary data figure min max
302 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 16.6 input setup and hold timings for 100-mhz bus operation table 65. input setup and hold timings for 100-mhz bus operation symbol parameter description preliminary data figure min max t 44 a[31:5] setup time 3.0 ns 108 t 45 a[31:5] hold time 1.0 ns 108 t 46 1 a20m# setup time 3.0 ns 108 t 47 1 a20m# hold time 1.0 ns 108 t 48 ahold setup time 3.5 ns 108 t 49 ahold hold time 1.0 ns 108 t 50 ap setup time 1.7 ns 108 t 51 ap hold time 1.0 ns 108 t 52 boff# setup time 3.5 ns 108 t 53 boff# hold time 1.0 ns 108 t 54 brdy# setup time 3.0 ns 108 t 55 brdy# hold time 1.0 ns 108 t 56 brdyc# setup time 3.0 ns 108 t 57 brdyc# hold time 1.0 ns 108 t 58 d[63:0] read data setup time 1.7 ns 108 t 59 d[63:0] read data hold time 1.5 ns 108 t 60 dp[7:0] read data setup time 1.7 ns 108 t 61 dp[7:0] read data hold time 1.5 ns 108 t 62 eads# setup time 3.0 ns 108 t 63 eads# hold time 1.0 ns 108 t 64 ewbe# setup time 1.7 ns 108 t 65 ewbe# hold time 1.0 ns 108 t 66 2 flush# setup time 1.7 ns 108 t 67 2 flush# hold time 1.0 ns 108 t 68 hold setup time 1.7 ns 108 t 69 hold hold time 1.5 ns 108 t 70 1 ignne# setup time 1.7 ns 108 t 71 1 ignne# hold time 1.0 ns 108 t 72 2 init setup time 1.7 ns 108
chapter 16 signal switching characteristics 303 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information t 73 2 init hold time 1.0 ns 108 t 74 1 intr setup time 1.7 ns 108 t 75 1 intr hold time 1.0 ns 108 t 76 inv setup time 1.7 ns 108 t 77 inv hold time 1.0 ns 108 t 78 ken# setup time 3.0 ns 108 t 79 ken# hold time 1.0 ns 108 t 80 na# setup time 1.7 ns 108 t 81 na# hold time 1.0 ns 108 t 82 2 nmi setup time 1.7 ns 108 t 83 2 nmi hold time 1.0 ns 108 t 84 2 smi# setup time 1.7 ns 108 t 85 2 smi# hold time 1.0 ns 108 t 86 1 stpclk# setup time 1.7 ns 108 t 87 1 stpclk# hold time 1.0 ns 108 t 88 wb/wt# setup time 1.7 ns 108 t 89 wb/wt# hold time 1.0 ns 108 notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must rema in asserted at least two clocks. table 65. input setup and hold timings for 100-mhz bus operation (continued) symbol parameter description preliminary data figure min max
304 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 16.7 output delay timings for 66-mhz bus operation table 66. output delay timings for 66-mhz bus operation symbol parameter description preliminary data figure min max t 6 a[31:3] valid delay 1.1 ns 6.3 ns 106 t 7 a[31:3] float delay 10.0 ns 107 t 8 ads# valid delay 1.0 ns 6.0 ns 106 t 9 ads# float delay 10.0 ns 107 t 10 adsc# valid delay 1.0 ns 7.0 ns 106 t 11 adsc# float delay 10.0 ns 107 t 12 ap valid delay 1.0 ns 8.5 ns 106 t 13 ap float delay 10.0 ns 107 t 14 apchk# valid delay 1.0 ns 8.3 ns 106 t 15 be[7:0]# valid delay 1.0 ns 7.0 ns 106 t 16 be[7:0]# float delay 10.0 ns 107 t 17 breq valid delay 1.0 ns 8.0 ns 106 t 18 cache# valid delay 1.0 ns 7.0 ns 106 t 19 cache# float delay 10.0 ns 107 t 20 d/c# valid delay 1.0 ns 7.0 ns 106 t 21 d/c# float delay 10.0 ns 107 t 22 d[63:0] write data valid delay 1.3 ns 7.5 ns 106 t 23 d[63:0] write data float delay 10.0 ns 107 t 24 dp[7:0] write data valid delay 1.3 ns 7.5 ns 106 t 25 dp[7:0] write data float delay 10.0 ns 107 t 26 ferr# valid delay 1.0 ns 8.3 ns 106 t 27 hit# valid delay 1.0 ns 6.8 ns 106 t 28 hitm# valid delay 1.1 ns 6.0 ns 106 t 29 hlda valid delay 1.0 ns 6.8 ns 106 t 30 lock# valid delay 1.1 ns 7.0 ns 106 t 31 lock# float delay 10.0 ns 107 t 32 m/io# valid delay 1.0 ns 5.9 ns 106 t 33 m/io# float delay 10.0 ns 107 t 34 pcd valid delay 1.0 ns 7.0 ns 106 t 35 pcd float delay 10.0 ns 107
chapter 16 signal switching characteristics 305 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information t 36 pchk# valid delay 1.0 ns 7.0 ns 106 t 37 pwt valid delay 1.0 ns 7.0 ns 106 t 38 pwt float delay 10.0 ns 107 t 39 scyc valid delay 1.0 ns 7.0 ns 106 t 40 scyc float delay 10.0 ns 107 t 41 smiact# valid delay 1.0 ns 7.3 ns 106 t 42 w/r# valid delay 1.0 ns 7.0 ns 106 t 43 w/r# float delay 10.0 ns 107 table 66. output delay timings for 66-mhz bus operation (continued) symbol parameter description preliminary data figure min max
306 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 16.8 input setup and hold timings for 66-mhz bus operation table 67. input setup and hold timings for 66-mhz bus operation symbol parameter description preliminary data figure min max t 44 a[31:5] setup time 6.0 ns 108 t 45 a[31:5] hold time 1.0 ns 108 t 46 1 a20m# setup time 5.0 ns 108 t 47 1 a20m# hold time 1.0 ns 108 t 48 ahold setup time 5.5 ns 108 t 49 ahold hold time 1.0 ns 108 t 50 ap setup time 5.0 ns 108 t 51 ap hold time 1.0 ns 108 t 52 boff# setup time 5.5 ns 108 t 53 boff# hold time 1.0 ns 108 t 54 brdy# setup time 5.0 ns 108 t 55 brdy# hold time 1.0 ns 108 t 56 brdyc# setup time 5.0 ns 108 t 57 brdyc# hold time 1.0 ns 108 t 58 d[63:0] read data setup time 2.8 ns 108 t 59 d[63:0] read data hold time 1.5 ns 108 t 60 dp[7:0] read data setup time 2.8 ns 108 t 61 dp[7:0] read data hold time 1.5 ns 108 t 62 eads# setup time 5.0 ns 108 t 63 eads# hold time 1.0 ns 108 t 64 ewbe# setup time 5.0 ns 108 t 65 ewbe# hold time 1.0 ns 108 t 66 2 flush# setup time 5.0 ns 108 t 67 2 flush# hold time 1.0 ns 108 t 68 hold setup time 5.0 ns 108 t 69 hold hold time 1.5 ns 108 t 70 1 ignne# setup time 5.0 ns 108 t 71 1 ignne# hold time 1.0 ns 108 t 72 2 init setup time 5.0 ns 108
chapter 16 signal switching characteristics 307 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information t 73 2 init hold time 1.0 ns 108 t 74 1 intr setup time 5.0 ns 108 t 75 1 intr hold time 1.0 ns 108 t 76 inv setup time 5.0 ns 108 t 77 inv hold time 1.0 ns 108 t 78 ken# setup time 5.0 ns 108 t 79 ken# hold time 1.0 ns 108 t 80 na# setup time 4.5 ns 108 t 81 na# hold time 1.0 ns 108 t 82 2 nmi setup time 5.0 ns 108 t 83 2 nmi hold time 1.0 ns 108 t 84 2 smi# setup time 5.0 ns 108 t 85 2 smi# hold time 1.0 ns 108 t 86 1 stpclk# setup time 5.0 ns 108 t 87 1 stpclk# hold time 1.0 ns 108 t 88 wb/wt# setup time 4.5 ns 108 t 89 wb/wt# hold time 1.0 ns 108 notes: 1. these level-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup and hold times must be met. if asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. these edge-sensitive signals can be asserted synchronously or asynchronously. to be sampled on a specific clock edge, setup a nd hold times must be met. if asserted asynchronously, they must have been negated at least two clocks prior to assertion and must rema in asserted at least two clocks. table 67. input setup and hold timings for 66-mhz bus operation (continued) symbol parameter description preliminary data figure min max
308 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 16.9 reset and test signal timing table 68. reset and configuration signals for 100-mhz bus operation symbol parameter description preliminary data figure min max t 90 reset setup time 1.7 ns 109 t 91 reset hold time 1.0 ns 109 t 92 reset pulse width, v cc and clk stable 15 clocks 109 t 93 reset active after v cc and clk stable 1.0 ms 109 t 94 1 notes: 1. bf[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of r eset. bf[2:0] setup time 1.0 ms 109 t 95 1 bf[2:0] hold time 2 clocks 109 t 96 intentionally left blank t 97 intentionally left blank t 98 intentionally left blank t 99 2 2. to be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which r eset is sampled negated. flush# setup time 1.7 ns 109 t 100 2 flush# hold time 1.0 ns 109 t 101 3 3. if asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of r eset. flush# setup time 2 clocks 109 t 102 3 flush# hold time 2 clocks 109
chapter 16 signal switching characteristics 309 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information table 69. reset and configuration signals for 66-mhz bus operation symbol parameter description preliminary data figure min max t 90 reset setup time 5.0 ns 109 t 91 reset hold time 1.0 ns 109 t 92 reset pulse width, v cc and clk stable 15 clocks 109 t 93 reset active after v cc and clk stable 1.0 ms 109 t 94 1 bf[2:0] setup time 1.0 ms 109 t 95 1 bf[2:0] hold time 2 clocks 109 t 96 intentionally left blank t 97 intentionally left blank t 98 intentionally left blank t 99 2 flush# setup time 5.0 ns 109 t 100 2 flush# hold time 1.0 ns 109 t 101 3 flush# setup time 2 clocks 109 t 102 3 flush# hold time 2 clocks 109 notes: 1. bf[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of r eset. 2. to be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which reset is sam- pled negated. 3. if asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of r eset.
310 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 70. tck waveform and trst# timing at 25 mhz symbol parameter description preliminary data figure min max tck frequency 25 mhz 110 t 103 tck period 40.0 ns 110 t 104 tck high time 14.0 ns 110 t 105 tck low time 14.0 ns 110 t 106 1,2 notes: 1. rise/fall times can be increased by 1.0 ns for each 10 mhz that tck is run below its maximum frequency of 25 mhz. 2. rise/fall times are measured between 0.8 v and 2.0 v. tck fall time 5.0 ns 110 t 107 tck rise time 5.0 ns 110 t 108 3 3. asynchronous. trst# pulse width 30.0 ns 111 table 71. test signal timing at 25 mhz symbol parameter description preliminary data figure min max t 109 1 notes: 1. parameter is measured from the tck rising edge. tdi setup time 5.0 ns 112 t 110 1 tdi hold time 9.0 ns 112 t 111 1 tms setup time 5.0 ns 112 t 112 1 tms hold time 9.0 ns 112 t 113 2 2. parameter is measured from the tck falling edge. tdo valid delay 3.0 ns 13.0 ns 112 t 114 2 tdo float delay 16.0 ns 112 t 115 2 all outputs (non-test) valid delay 3.0 ns 13.0 ns 112 t 116 2 all outputs (non-test) float delay 16.0 ns 112 t 117 1 all inputs (non-test) setup time 5.0 ns 112 t 118 1 all inputs (non-test) hold time 9.0 ns 112
chapter 16 signal switching characteristics 311 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 16.10 timing diagrams figure 105. key to timing diagrams must be steady can change from high to low can change from low to high (does not apply) dont care, any change permitted steady changing from high to low changing from low to high changing, state unknown center line is high impedance state waveform inputs outputs
312 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 106. output valid delay timing figure 107. maximum float delay timing figure 108. input setup and hold timing min max valid n +1 t v valid n clk output signal t x t x 1.5 v note: for symbols t v listed in table 64 on page 300 and table 66 on page 304, where: v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42 t x t x t x valid t x t v min output signal t f clk 1.5 v note: for symbols t v and t f listed in table 64 on page 300 and table 66 on page 304, where: v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42 f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43 clk t x t x t x t x input signal t s t h 1.5 v note: for symbols t s and t h listed in table 65 on page 302 and table 67 on page 306, where: s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88 h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
chapter 16 signal switching characteristics 313 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 109. reset and configuration timing t x clk reset t x t 90 flush# (synchronous) 1.5 v 1.5 v 1.5 v ? ? ? t 92, 93 t 91 t 99 t 100 ? ? ? bf[2:0] (asynchronous) t 94 ? ? ? t 95 flush# (asynchronous) t 101 t 102 ? ? ? ? ? ?
314 signal switching characteristics chapter 16 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 110. tck waveform figure 111. trst# timing figure 112. test signal timing diagram t 107 2.0 v 1.5 v 0.8 v t 10 5 t 10 6 t 103 t 10 4 1.5 v t 10 8 tck tdi, tms tdo output signals input signals t 10 3 t 10 9, 111 t 110, 112 t 113 t 115 t 116 t 117 t 118 t 114 1.5 v
chapter 17 thermal design 315 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 17 thermal design 17.1 package thermal specifications the AMD-K6-IIIE+ processor operating specification calls for the case temperature (t c ) to be in the range of 0c to 70c for standard-power devices and 0c to 85c for low-power devices. the ambient temperature (t a ) is not specified as long as the case temperature is not violated. the case temperature must be measured on the top center of the package. table 72 and table 73 on page 316 show the processor thermal specifications for the low-power and standard power AMD-K6-IIIE+ devices, respectively.
316 thermal design chapter 17 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 113 on page 317 shows the thermal model of a processor with a passive thermal solution. the case-to-ambient temperature (t ca ) can be calculated from the following equation: t ca = p max ? q ca = p max ? ( q if + q sa ) where: p max = maximum power consumption q ca = case-to-ambient thermal resistance q if = interface material thermal resistance q sa = sink-to-ambient thermal resistance table 72. package thermal specification for low-power amd-k6?- iii e+ devices q jc junction-case maximum thermal power 400 mhz 450 mhz 500 mhz 1.0 c/w 9.50 w 12.00 w 14.50 w stop grant mode 2.50 w stop clock mode 1.60 w 1.90 w t c case temperature 0cC85 table 73. package thermal specification for standard-power amd-k6?- iii e+ devices q jc junction-case maximum thermal power 400 mhz 450 mhz 500 mhz 550 mhz 1.0c/w 16.50 w 17.50 w 18.50 w 19.50 w stop grant mode 4.50 w stop clock mode 4.00 w t c case temperature 0cC70c
chapter 17 thermal design 317 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 113. thermal model (cpga package) figure 114 illustrates the case-to-ambient temperature (t ca ) in relation to the power consumption (x-axis) and the thermal resistance (y-axis). if the power consumption and case temperature are known, the thermal resistance ( q ca ) requirement can be calculated for a given ambient temperature (t a ) value. figure 114. power consumption and thermal resistance (cpga package) temperature thermal q sa q ca q if (c/w) (ambient) case sink t ca resistance : : : : : : : : : : power consumption (watts) ghj& ghj& ghj& ghj& case-to-ambient temperature (t c - t a ) q ca thermal resistance ( c/w) t ca = t c - t a
318 thermal design chapter 17 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information the thermal resistance of a heatsink is determined by the heat dissipation surface area, the material and shape of the heatsink, and the airflow volume across the heatsink. in general, the larger the surface area the lower the thermal resistance. the required thermal resistance of a heatsink ( q sa ) can be calculated using the following example: if: t c = 70c t a = 45c p max = 19.50w then: thermal grease is recommended as interface material because it provides the lowest thermal resistance ( @ 0.20c/w). the required thermal resistance ( q sa ) of the heatsink in this example is calculated as follows: q sa = q ca C q if = 1.28 C 0.20 = 1.08c/w heat dissipation path figure 115 illustrates the heat dissipation path of the processor. due to the lower thermal resistance between the processor die junction and case, most of the heat generated by the processor is transferred from the top surface of the case. the small amount of heat generated from the bottom side of the processor where the processor socket blocks the convection can be safely ignored. figure 115. processor heat dissipation path q ca t c t a C p max ------------------- - y ?? ? 25 ? c 19.50w ------------------- 1.28 ? cw ? == thin lid case temperature ambient temperature
chapter 17 thermal design 319 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 17.2 measuring case temperature the processor case temperature is measured to ensure that the thermal solution meets the processors operational specification. this temperature should be measured on the top center of the package, where most of the heat is dissipated. figure 116 shows the correct location for measuring the case temperature. the tip of the thermocouple should be secured to the package surface with a small amount of thermally conductive epoxy. it is also recommended to secure a second location along the thermocouple to avoid any movement during testing. if a heatsink is installed while measuring, the thermocouple must be installed into the heatsink via a small hole drilled through the heatsink base (for example, 1/16 of an inch). secure the thermocouple to the base of the heatsink by filling the small hole with thermal epoxy, allowing the tip of the thermocouple to protrude the epoxy and touch the top of the processor case. figure 116. measuring case temperature 17.3 layout and airflow considerations voltage regulator a voltage regulator is required to support the lower voltage (3.3 v and lower) to the processor. in most applications, the voltage regulator is designed with power transistors. as a result, additional heatsinks are required to dissipate the heat from the power transistors. figure 117 on page 320 shows the thermocouple thermally conductive epoxy
320 thermal design chapter 17 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information voltage regulator placed parallel to the processor with the airflow aligned with the devices. with this alignment, the heat generated by the voltage regulator has minimal effect on the processor. figure 117. voltage regulator placement a heatsink and fan combination can deliver much better thermal performance than a heatsink alone. more importantly, with a fan/sink the airflow requirements in a system design are not as critical. a unidirectional heatsink with a fan moves air from the top of the heatsink to the side. in this case, the best location for the voltage regulator is on the side of the processor in the path of the airflow exiting the fan sink (see figure 118 on page 321). this location guarantees that the heatsinks on both the processor and the regulator receive adequate air circulation. processor airflow voltage regulator
chapter 17 thermal design 321 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information figure 118. airflow for a heatsink with fan airflow management in a system design complete airflow management in a system is important. in addition to the volume of air, the path of the air is also important. figure 119 shows the airflow in a dual-fan system. the fan in the front end pulls cool air into the system through intake slots in the chassis. the power supply fan forces the hot air out of the chassis. the thermal performance of the heatsink can be maximized if it is located in the shaded area, where it receives greatest benefit from this air exchange system. figure 119. airflow path in a dual-fan system airflow ideal areas for voltage regulator drive bays p/s vents v e n t s fan fan main board front
322 thermal design chapter 17 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information figure 120 shows the airflow management in a system using the atx form-factor. the orientation of the power supply fan and the motherboard are modified in the atx platform design. the power supply fan pulls cool air through the chassis and across the processor. the processor is located near the power supply fan, where it can receive adequate airflow without an auxiliary fan. the arrangement significantly improves the airflow across the processor with minimum installation cost. figure 120. airflow path in an atx form-factor system for more information about thermal design considerations, see the amd-k6 ? processor thermal solution design application note , order# 21085. p/s main board drive bays f a n
chapter 18 pin designations 323 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 18 pin designations this chapter includes pin connection diagrams and pin designation tables for each of two packages, the ceramic pin grid array (cpga) and the organic ball grid array (obga). the pin designation diagrams include the following annotations: note that the obga package includes additional pins not supported on the cpga package. table 74 shows the pin differences between the two packages. control/parity pins address pins v ss pins t test pins v cc2 pins nc, inc (internal no connect) pins v cc3 pins rsvd (reserved) pins data pins table 74. pin differences between the cpga and obga packages pin cpga package ogba package comment vcc2det supported not supported vcc2h/l# supported not supported vid[4:0] supported on low- power versions only supported on low- power versions only these pins are no-connects (nc) on standard-power versions for both packages. v cc2 28 37 v cc3 32 26 v ss 68 99 no connects 13 1 8 2 notes: 1. standard-power versions only, since the vid[4:0] outputs are not supported. 2. low-power versions only. 13 1 8 2 internal no connects 71 reserved 14 16
324 pin designations chapter 18 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 18.1 pins designations for cpga package notes: the vid[4:0] outputs are supported on low-power versions only. these pins are defined as no-connects on standard-power versions . figure 121. cpga connection diagram (top-side view) a8 rsvd rsvd rsvd rsvd bf2 bf1 bf0 tdo a28 a30 a10 a20 be7# be6# be5# be4# be3# be2# be1# a20m# ads# lock# pcd be0# d/c# pwt apchk# eads# hlda brdy# brdyc# adsc# ewbe# boff# hold rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd ap m/io# pchk# ahold# rsvd rsvd d0 d2 d1 d3 tdi d4 d5 d7 d12 d19 d21 dp1 d17 d20 d22 d18 d14 d15 d10 d16 d13 dp0 d9 d11 d6 d24 d23 dp2 d25 d8 d26 d28 d27 d30 d29 dp3 d31 d33 d32 d35 d34 d37 d39 d42 d40 d36 d38 dp4 d45 d44 dp5 d46 d53 d60 dp7 d43 d41 d49 d51 d58 d59 d62 d61 d63 d57 d55 d50 d47 d56 dp6 d54 d52 d48 a6 a26 a29 breq vcc2det vcc2h/l# wb/wt# 30 28 20 18 10 8 top view data pins 16 9 19 6 26 29 36 v cc 2 v cc 3 v ss ferr# d v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 a23 a27 a21 init smi# nmi inc nc stpclk# vid0 inc ignne# trst# tms inc nc a22 a25 a24 a31 a7 a3 a4 a5 a9 a13 a14 a15 a11 a12 a16 a17 a19 intr reset clk scyc nc nc inc flush# hit# inv ken# na# cache# smiact# hitm# w/r# inc inc inc nc v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss a18 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v ss v cc 2 tck v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 37 35 34 33 32 31 27 25 24 23 22 21 17 14 13 12 11 15 7 5 4 3 2 1 30 28 20 18 10 8 16 9 19 6 26 29 36 37 35 34 33 32 31 27 25 24 23 22 21 17 14 13 12 11 15 7 5 4 3 2 1 q acegjln s w u y aa ac ae ag aj al an bd p abad fhkm rtvxz afahakam q acegjln s w u y aa ac ae ag aj al an bd p abad fhkm rtvxz afahakam vid2 nc nc vid1 vid3 vid4 nc
chapter 18 pin designations 325 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information notes: the vid[4:0] outputs are supported on low-power versions only. these pins are defined as no-connects on standard-power versions . figure 122. cpga connection diagram (bottom-side view) bottom view hold hlda ads# breq apchk# lock# pchk# pcd d/c# pwt ap be1# be2# be3# be5# be0# be4# be6# rsvd rsvd rsvd rsvd rsvd be7# rsvd rsvd adsc# eads# brdy# brdyc# boff# ewbe# rsvd rsvd rsvd ahold m/io# ferr# wb/wt# ken# smiact# a20m# reset a20 a19 a17 a18 a15 hitm# vcc2det d63 dp7 d61 d57 d59 d58 d55 d53 d62 d60 d56 dp5 d51 dp6 d54 d44 d42 d39 d33 d52 d49 d40 d35 dp3 d37 d46 d47 d45 dp4 d48 d43 d41 d38 d36 d34 d32 d31 d27 d29 d25 dp2 d30 d28 d26 d23 rsvd rsvd rsvd d19 dp1 d12 d24 d21 d17 d3 d5 dp0 d6 d14 d11 d15 d7 d10 d9 d20 d22 d13 d16 d18 d4 d2 d0 tdo tdi d1 d8 tck tms trst# bf0 bf1 bf2 stpclk# ignne# intr smi# nmi init inc a26 vid1 inc inc inc vcc2h/l# inc flush# inc nc a9 a16 a6 a30 a29 a28 a10 an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a a8 v cc 2 v cc 2 v cc 2 v cc 2 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss 67891011121314 171819202122232425262728293031323334353637 12345 1516 67891011121314 171819202122232425262728293031323334353637 12345 1516 v ss v ss v ss v ss v ss cache# inv na# v ss v ss v ss v ss v ss v ss v ss nc nc nc scyc w/r# v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 v ss a5 a31 a25 a22 a24 a27 a23 a21 a3 a7 a4 a12 a13 a14 a11 clk vid0 inc hit# v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 nc v cc 3 v cc 3 v cc 3 v cc 3 v cc 3 rsvd nc nc vid2 vid3 vid4 nc
326 pin designations chapter 18 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information notes: 1. the vid[4:0] pins are supported on low-power versions only. these pins are defined as no-connects on standard-power v ersions. table 75. cpga pin designations by functional grouping pin name pin number pin name pin number pin name pin number pin name pin number control address data data a20m# ak-08 a3 al-35 d0 k-34 d52 e-03 ads# aj-05 a4 am-34 d1 g-35 d53 g-05 adsc# am-02 a5 ak-32 d2 j-35 d54 e-01 ahold v-04 a6 an-33 d3 g-33 d55 g-03 apchk# ae-05 a7 al-33 d4 f-36 d56 h-04 be0# al-09 a8 am-32 d5 f-34 d57 j-03 be1# ak-10 a9 ak-30 d6 e-35 d58 j-05 be2# al-11 a10 an-31 d7 e-33 d59 k-04 be3# ak-12 a11 al-31 d8 d-34 d60 l-05 be4# al-13 a12 al-29 d9 c-37 d61 l-03 be5# ak-14 a13 ak-28 d10 c-35 d62 m-04 be6# al-15 a14 al-27 d11 b-36 d63 n-03 be7# ak-16 a15 ak-26 d12 d-32 test bf0 y-33 a16 al-25 d13 b-34 tck m-34 bf1 x-34 a17 ak-24 d14 c-33 tdi n-35 bf2 w-35 a18 al-23 d15 a-35 tdo n-33 boff# z-04 a19 ak-22 d16 b-32 tms p-34 brdy# x-04 a20 al-21 d17 c-31 trst# q-33 brdyc# y-03 a21 af-34 d18 a-33 parity breq aj-01 a22 ah-36 d19 d-28 ap ak-02 cache# u-03 a23 ae-33 d20 b-30 dp0 d-36 clk ak-18 a24 ag-35 d21 c-29 dp1 d-30 d/c# ak-04 a25 aj-35 d22 a-31 dp2 c-25 eads# am-04 a26 ah-34 d23 d-26 dp3 d-18 ewbe# w-03 a27 ag-33 d24 c-27 dp4 c-07 ferr# q-05 a28 ak-36 d25 c-23 dp5 f-06 flush# an-07 a29 ak-34 d26 d-24 dp6 f-02 hit# ak-06 a30 am-36 d27 c-21 dp7 n-05 hitm# al-05 a31 aj-33 d28 d-22 voltage id 1 hlda aj-03 d29 c-19 vid4 e-17 hold ab-04 d30 d-20 vid3 e-25 ignne# aa-35 d31 c-17 vid2 r-34 init aa-33 d32 c-15 vid1 an-35 intr ad-34 d33 d-16 vid0 ah-32 inv u-05 d34 c-13 ken# w-05 d35 d-14 lock# ah-04 d36 c-11 m/io# t-04 d37 d-12 na# y-05 d38 c-09 nmi ac-33 d39 d-10 pcd ag-05 d40 d-08 pchk# af-04 d41 a-05 pwt al-03 d42 e-09 reset ak-20 d43 b-04 scyc al-17 d44 d-06 smi# ab-34 d45 c-05 smiact# ag-03 d46 e-07 stpclk# v-34 d47 c-03 vcc2det al-01 d48 d-04 vcc2h/l# an-05 d49 e-05 w/r# am-06 d50 d-02 wb/wt# aa-05 d51 f-04
chapter 18 pin designations 327 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information notes: 1. these pins are no-connects on standard-power versions only. they are defined as vid[4:0] on low-power versions. see p age 326. table 76. cpga pin designations for no connect, reserved, power, and ground pins pin numbers no connect (nc) v cc2 v cc3 v ss v ss a-37 a-07 a-19 a-03 aj-27 c-01 a-09 a-21 b-06 aj-31 e-17 1 a-11 a-23 b-08 aj-37 e-25 1 a-13 a-25 b-10 al-37 r-34 1 a-15 a-27 b-12 am-08 s-33 a-17 a-29 b-14 am-10 s-35 b-02 e-21 b-16 am-12 w-33 e-15 e-27 b-18 am-14 ah-32 1 g-01 e-37 b-20 am-16 aj-15 j-01 g-37 b-22 am-18 aj-23 l-01 j-37 b-24 am-20 al-19 n-01 l-33 b-26 am-22 an-35 1 q-01 l-37 b-28 am-24 internal no connect (inc) s-01 n-37 e-11 am-26 h-34 u-01 q-37 e-13 am-28 y-35 w-01 s-37 e-19 am-30 z-34 y-01 t-34 e-23 an-37 ac-35 aa-01 u-33 e-29 al-07 ac-01 u-37 e-31 an-01 ae-01 w-37 h-02 an-03 ag-01 y-37 h-36 reserved (rsvd) aj-11 aa-37 k-02 j-33 an-09 ac-37 k-36 l-35 an-11 ae-37 m-02 p-04 an-13 ag-37 m-36 q-03 an-15 aj-19 p-02 q-35 an-17 aj-29 p-36 r-04 an-19 an-21 r-02 s-03 an-23 r-36 s-05 an-25 t-02 aa-03 an-27 t-36 ac-03 an-29 u-35 ac-05 v-02 ad-04 v-36 ae-03 x-02 ae-35 x-36 z-02 z-36 ab-02 ab-36 ad-02 ad-36 af-02 af-36 ah-02 aj-07 aj-09 aj-13 aj-17 aj-21 aj-25
328 pin designations chapter 18 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 18.2 pins designations for obga package notes: there are three pads missing on each corner of the obga package due to manufacturing requirements. the vid[4:0] outputs are supported on low-power versions only. these pins are defined as no-connects on standard-power versions . figure 123. obga connection diagram (top-side view) 12345678910111213141516171819 a d52 dp5 d47 d45 d40 d39 d37 d33 vid4 d29 d28 d26 d23 d20 d16 a b d51 v ss nc v ss d44 v ss d41 v ss d32 v ss d30 v cc3 dp2 v ss d19 v cc3 d17 b c dp6 v cc2 d54 d50 d49 d46 d43 dp4 d38 d35 dp3 d27 d25 d24 vid3 d22 dp1 v ss d18 c d d59 d56 d58 v cc2 d53 d48 d42 v ss d36 d34 d31 v ss d21 d13 d15 v ss d14 d12 d10 d e d60 v ss d55 d57 v cc2 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss d7 d8 v cc3 d9 e f dp7 d62 d61 d63 v ss v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v ss v ss v cc3 v ss d11 d3 d5 d6 f g rsvd v cc2 rsvd ferr# v cc2 v ss v ss v ss v ss v ss v ss v ss v ss v ss v cc3 rsvd dp0 v ss d1 g h rsvd rsvd rsvd v cc2 v ss v cc2 v cc2 v ss v ss v cc3 v cc3 v cc3 v cc3 v cc3 v ss v cc3 d4 d0 d2 h j inv v ss m/io# cache# v cc2 v ss v ss v ss v ss v ss v ss v ss v ss v ss v cc3 t tdo rsvd v cc3 t tck j k brdy# ken# ewbe# ahold v ss v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v ss v ss v cc3 v ss rsvd t trst# t tms t tdi k l brdyc# v cc2 boff# na# v cc2 v ss v ss v ss v ss v ss v ss v ss v ss v ss v cc3 v ss nc v ss vid2 l m rsvd wb/wt# hold v cc2 v ss v cc2 v cc2 v cc2 v cc2 v cc2 v cc2 v ss v ss v cc3 v ss nc bf1 stpclk# nc m n rsvd v ss rsvd rsvd v cc2 v ss v ss v ss v ss v ss v ss v ss v ss v ss v cc3 inc bf0 v cc3 bf2 n p rsvd smiact# pchk# breq v ss v cc2 v ss rsvd v ss v ss v cc3 v cc3 v ss v cc3 v ss intr init smi# ignne# p r apchk# v cc2 ap pcd v cc2 v ss v ss rsvd v ss v cc3 v ss v ss v cc3 v ss v ss a28 nmi v ss rsvd r t lock# hlda adsc# v cc2 nc v ss flush# be5# nc a20 a16 a8 a4 a3 a27 v ss a21 a24 a22 t u ads# v ss d/c# hitm# w/r# be0# be4# be6# clk a19 nc a15 a13 a7 a31 a29 a26 v cc3 a23 u v pwt v cc2 eads# v ss be2# v cc2 be7# v ss a18 v cc3 a10 v ss a6 v cc3 a30 v ss a25 v w hit# a20m# be1# be3# nc scyc reset a17 a14 a12 a11 a9 a5 vid1 vid0 w 12345678910111213141516171819
chapter 18 pin designations 329 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information notes: there are three pads missing on each corner of the obga package due to manufacturing requirements. the vid[4:0] outputs are supported on low-power versions only. these pins are defined as no-connects on standard-power versions . figure 124. obga connection diagram (bottom-side view) abcde fgh j k lmnprtuvw 1 dp6 d59 d60 dp7 rsvd rsvd inv brdy# brdyc# rsvd rsvd rsvd apchk# lock# ads# 1 2 d51 v cc2 d56 v ss d62 v cc2 rsvd v ss ken# v cc2 wb/wt# v ss smiact# v cc2 hlda v ss pwt 2 3 d52 v ss d54 d58 d55 d61 rsvd rsvd m/io# ewbe# boff# hold rsvd pchk# ap adsc# d/c# v cc2 hit# 3 4 dp5 nc d50 v cc2 d57 d63 ferr# v cc2 cache# ahold na# v cc2 rsvd breq pcd v cc2 hitm# eads# a20m# 4 5 d47 v ss d49 d53 v cc2 v ss v cc2 v ss v cc2 v ss v cc2 v ss v cc2 v ss v cc2 nc w/r# v ss be1# 5 6 d45 d44 d46 d48 v ss v cc2 v ss v cc2 v ss v cc2 v ss v cc2 v ss v cc2 v ss v ss be0# be2# be3# 6 7 d40 v ss d43 d42 v ss v cc2 v ss v cc2 v ss v cc2 v ss v cc2 v ss v ss v ss flush# be4# v cc2 nc 7 8 d39 d41 dp4 v ss v ss v cc2 v ss v ss v ss v cc2 v ss v cc2 v ss rsvd rsvd be5# be6# be7# scyc 8 9 d37 v ss d38 d36 v ss v cc2 v ss v ss v ss v cc2 v ss v cc2 v ss v ss v ss nc clk v ss reset 9 10 d33 d32 d35 d34 v ss v cc2 v ss v cc3 v ss v cc2 v ss v cc2 v ss v ss v cc3 a20 a19 a18 a17 10 11 vid4 v ss dp3 d31 v ss v cc2 v ss v cc3 v ss v cc2 v ss v cc2 v ss v cc3 v ss a16 nc v cc3 a14 11 12 d29 d30 d27 v ss v ss v ss v ss v cc3 v ss v ss v ss v ss v ss v cc3 v ss a8 a15 a10 a12 12 13 d28 v cc3 d25 d21 v ss v ss v ss v cc3 v ss v ss v ss v ss v ss v ss v cc3 a4 a13 v ss a11 13 14 d26 dp2 d24 d13 v ss v cc3 v ss v cc3 v ss v cc3 v ss v cc3 v ss v cc3 v ss a3 a7 a6 a9 14 15 d23 v ss vid3 d15 v ss v ss v cc3 v ss v cc3 v ss v cc3 v ss v cc3 v ss v ss a27 a31 v cc3 a5 15 16 d20 d19 d22 v ss d7 d11 rsvd v cc3 t tdo rsvd v ss nc inc intr a28 v ss a29 a30 vid1 16 17 d16 v cc3 dp1 d14 d8 d3 dp0 d4 rsvd t trst# nc bf1 bf0 init nmi a21 a26 v ss vid0 17 18 d17 v ss d12 v cc3 d5 v ss d0 v cc3 t tms v ss stpclk# v cc3 smi# v ss a24 v cc3 a25 18 19 d18 d10 d9 d6 d1 d2 t tck t tdi vid2 nc bf2 ignne# rsvd a22 a23 19 abcde fgh j k lmnprtuvw
330 pin designations chapter 18 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information notes: 1. the vid[4:0] pins are supported on low-power versions only. these pins are defined as no-connects on standard-power v ersions. table 77. obga pin designations by functional grouping pin name pin number pin name pin number pin name pin number pin name pin number control address data data a20m# w4 a3 t14 d0 h18 d52 a3 ads# u1 a4 t13 d1 g19 d53 d5 adsc# t3 a5 w15 d2 h19 d54 c3 ahold k4 a6 v14 d3 f17 d55 e3 apchk# r1 a7 u14 d4 h17 d56 d2 be0# u6 a8 t12 d5 f18 d57 e4 be1# w5 a9 w14 d6 f19 d58 d3 be2# v6 a10 v12 d7 e16 d59 d1 be3# w6 a11 w13 d8 e17 d60 e1 be4# u7 a12 w12 d9 e19 d61 f3 be5# t8 a13 u13 d10 d19 d62 f2 be6# u8 a14 w11 d11 f16 d63 f4 be7# v8 a15 u12 d12 d18 test bf0 n17 a16 t11 d13 d14 tck j19 bf1 m17 a17 w10 d14 d17 tdi k19 bf2 n19 a18 v10 d15 d15 tdo j16 boff# l3 a19 u10 d16 a17 tms k18 brdy# k1 a20 t10 d17 b18 trst# k17 brdyc# l1 a21 t17 d18 c19 parity breq p4 a22 t19 d19 b16 ap r3 cache# j4 a23 u19 d20 a16 dp0 g17 clk u9 a24 t18 d21 d13 dp1 c17 d/c# u3 a25 v18 d22 c16 dp2 b14 eads# v4 a26 u17 d23 a15 dp3 c11 ewbe# k3 a27 t15 d24 c14 dp4 c8 ferr# g4 a28 r16 d25 c13 dp5 a4 flush# t7 a29 u16 d26 a14 dp6 c1 hit# w3 a30 v16 d27 c12 dp7 f1 hitm# u4 a31 u15 d28 a13 voltage id 1 hlda t2 d29 a12 vid0 w17 hold m3 d30 b12 vid1 w16 ignne# p19 d31 d11 vid2 l19 init p17 d32 b10 vid3 c15 intr p16 d33 a10 vid4 a11 inv j1 d34 d10 ken# k2 d35 c10 lock# t1 d36 d9 m/io# j3 d37 a9 na# l4 d38 c9 nmi r17 d39 a8 pcd r4 d40 a7 pchk# p3 d41 b8 pwt v2 d42 d7 reset w9 d43 c7 scyc w8 d44 b6 smi# p18 d45 a6 smiact# p2 d46 c6 stpclk# m18 d47 a5 w/r# u5 d48 d6 wb/wt# m2 d49 c5 d50 c4 d51 b2
chapter 18 pin designations 331 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information notes: 1. these pins are no-connects on standard-power versions only. they are defined as vid[4:0] on low-power versions. see p age 330. table 78. obga pin designations for no connect, reserved, power, and ground pins pin numbers no connect (nc) v cc2 v cc3 v ss v ss a11 1 c2 b13 b3 k13 b4 d4 b17 b5 k15 c15 1 e5 e18 b7 l6 l17 f6 f14 b9 l7 l19 1 f7 g15 b11 l8 m16 f8 h10 b15 l9 m19 f9 h11 c18 l10 t5 f10 h12 d8 l11 t9 f11 h13 d12 l12 u11 g2 h14 d16 l13 w7 g5 h16 e2 l14 w16 1 h4 j15 e6 l16 w17 1 h6 j18 e7 l18 internal no connect (inc) h7 k14 e8 m5 n16 j5 l15 e9 m12 reserved (rsvd) k6 m14 e10 m13 g1 k7 n15 e11 m15 g3 k8 n18 e12 n2 g16 k9 p11 e13 n6 h1 k10 p12 e14 n7 h2 k11 p14 e15 n8 h3 l2 r10 f5 n9 j17 l5 r13 f12 n10 k16 m4 u18 f13 n11 m1 m6 v11 f15 n12 n1 m7 v15 g6 n13 n3 m8 g7 n14 n4 m9 g8 p5 p1 m10 g9 p7 p8 m11 g10 p9 r8 n5 g11 p10 r19 p6 g12 p13 r2 g13 p15 r5 g14 r6 t4 g18 r7 v3 h5 r9 v7 h8 r11 h9 r12 h15 r14 j2 r15 j6 r18 j7 t6 j8 t16 j9 u2 j10 v5 j11 v9 j12 v13 j13 v17 j14 k5 k12
332 pin designations chapter 18 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information
chapter 19 package specifications 333 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 19 package specifications 19.1 321-pin staggered cpga package specification figure 125. 321-pin staggered cpga package specification
334 package specifications chapter 19 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information 19.2 349-ball obga package specification figure 126. 349-ball obga package specification dwg rev. aa.04; 08/00
chapter 20 ordering information 335 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information 20 ordering information standard amd-k6?- iii e+ embedded processor products amd standard products are available in several operating ranges. the ordering part number (opn) is formed by a combination of the elements below. see table 79 on page 336 for valid ordering part number combinations. a amd-k6- iii e+ package type family/core amd-k6- iii e+ case temperature r= 0cC70c z= 0cC85c 550 performance rating 550 500 operating voltage t = 1.5 vC1.7 v (core)/ 3.135 vC3.6 v (i/o) p = 1.6 vC1.8 v (core)/ 3.135 vC3.6 v (i/o) n = 1.7 vC1.9 v (core)/ 3.135 vC3.6 v (i/o) c = 1.9 vC2.1 v (core)/ 3.135 vC3.6 v (i/o) c r 450 400 a = 321-pin cpga i = 349-ball obga
336 ordering information chapter 20 amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information table 79. amd-k6?- iii e+ embedded processor valid ordering part number combinations device type opn 1 notes: 1. this table lists configurations planned to be supported in volume for this device. consult the local amd sales office to conf irm availability of specific valid combinations and to check on newly-released combinations. package type operating voltage case temperature maximum cpu/bus frequency low power amd-k6- iii e+400atz 321-pin cpga 1.5 vC1.7 v (core) 3.135 vC3.6 v (i/o) 0cC85c 400 mhz/100 mhz amd-k6- iii e+450apz 321-pin cpga 1.6 vC1.8 v (core) 3.135 vC3.6 v (i/o) 0cC85c 450 mhz/100 mhz amd-k6- iii e+500anz 321-pin cpga 1.7 vC1.9 v (core) 3.135 vC3.6 v (i/o) 0cC85c 500 mhz/100 mhz amd-k6- iii e+400itz 349-ball obga 1.5 vC1.7 v (core) 3.135 vC3.6 v (i/o) 0cC85c 400 mhz/100 mhz standard power amd-k6- iii e+400acr 321-pin cpga 1.9 vC2.1 v (core) 3.135 vC3.6 v (i/o) 0cC70c 400 mhz/100 mhz amd-k6- iii e+450acr 321-pin cpga 1.9 vC2.1 v (core) 3.135 vC3.6 v (i/o) 0cC70c 450 mhz/100 mhz amd-k6- iii e+500acr 321-pin cpga 1.9 vC2.1 v (core) 3.135 vC3.6 v (i/o) 0cC70c 500 mhz/100 mhz amd-k6- iii e+550acr 321-pin cpga 1.9 vC2.1 v (core) 3.135 vC3.6 v (i/o) 0cC70c 550 mhz/100 mhz amd-k6- iii e+400icr 349-ball obga 1.9 vC2.1 v (core) 3.135 vC3.6 v (i/o) 0cC70c 400 mhz/100 mhz amd-k6- iii e+450icr 349-ball obga 1.9 vC2.1 v (core) 3.135 vC3.6 v (i/o) 0cC70c 450 mhz/100 mhz
index 337 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information index numerics 0.18-micron process technology . . . . . . . . . . . . . . . . . . . . . . . 7 100-mhz bus clock switching characteristics . . . . . . . . . . . . . . . . . . . . 298 frontside. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 8 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 302 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 8 321-pin staggered cpga package . . . . . . . . . . . . . . . . . . . . . 2 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 349-ball obga package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 3dnow!? technology. . . . . . . 2 , 5 , 7 , 15 , 17 , 19 , 21 C 24 , 127 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 init state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 instruction compatibility, floating-point and . . . . . . . . . 240 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 C 90 , 240 prefetch instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 220 register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 software prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 66-mhz bus clock switching characteristics . . . . . . . . . . . . . . . . . . . . 299 input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 306 output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 a a[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 a20m# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 , 242 masking cache accesses with . . . . . . . . . . . . . . . . . . . . . . 227 absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 accelerated graphic port (agp) . . . . . . . . . . . . . . . . . . . . . . . 8 acknowledge, interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 address bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 , 109 a[31:3] signals] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 address hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 address strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ahold restriction . . . . . . . . . . . . . . . . . . . 174 , 178 , 180 coherencey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 C 99 generation sequence during bursts (table) . . . . . . . . . . 162 hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 parity check signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 parity signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ads# signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 adsc# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ahold -initiated inquire hit to modified line. . . . . . . . . . . . . . . 178 -initiated inquire hit to shared or exclusive line . . . . . . 176 -initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 ahold signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 , 280 airflow consideration in layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 heatsink with fan (figure). . . . . . . . . . . . . . . . . . . . . . . . . 321 management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 path in a dual-fan system (figure) . . . . . . . . . . . . . . . . . . 321 path in an atx form-factor system (figure) . . . . . . . . . . 322 aligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 allocate, write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 amd powernow!? technology . . . . . . . . . . . 6 , 143 , 151 , 277 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 dynamic core voltage control . . . . . . . . . . . . . . . . . . . . . .151 enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 enhanced power management register (epmr) . . . . . . 144 epm 16-byte i/o block . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 epm stop grant state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 i/o base address definition. . . . . . . . . . . . . . . . . . . . . . . . 145 processor state observability register (psor) . . . . . . . . 148 smm handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 voltage identification signals . . . . . . . . . . . . . . . . . 137 , 151 ap signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 apchk# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 asserted signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 b backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 bdc bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 be[7:0]# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 bf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 199 , 285 bios, enhanced power management. . . . . . . . . . . . . . . . . . 145 bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 boff# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 , 182 locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 boundary-scan bit definitions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 br . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 branch execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 7 , 15 , 23 , 26 target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 brdy# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 brdyc# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 breq signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 bsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 burst pipelined burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 ready copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 , 200 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 writeback due to cache-line replacement . . . . . . . .164 C 165 bus 100-mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 , 8 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 a[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
338 index amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 external address strobe signal. . . . . . . . . . . . . . . . . . . 109 hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 , 174 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 C 99 strobe copy signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 168 backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 byte enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 C 197 aligned transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 definitions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 order during misaligned i/o transfers (table) . . . . . . 167 order during misaligned memory transfers (table). . 160 special . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 , 190 data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 , 103 , 174 ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 aligned transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 byte enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 d[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 memory reads and writes. . . . . . . . . . . . . . . . . . . . . . . 158 misaligned transfers . . . . . . . . . . . . . . . . . . . . . . . 129 , 184 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 , 125 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 frequency signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 hold request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 lock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 request signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 states address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 data-na# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 state machine (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 155 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 bvc field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 definition (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 bvcm bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 bypass register (br) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 c cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 branch target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 burst writeback cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 cacheable access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . 46 , 211 , 251 , 263 enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 , 191 inhibiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 , 263 inquire cycles . . . . . . . . . . . . . . . . . . . . . . . . . 168 , 174 , 178 inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 instruction fetch and decode . . . . . . . . . . . . . . . . . . . . . . . 17 instruction prefetch. . . . . . . . . . . . . . . . . . . . . . . 16 C 17 , 220 l1 cache cache-line replacement. . . . . . . . . . . . . . . . . . . . . . . . . 214 coherency states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 data cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . 207 instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 instruction cache line (figure) . . . . . . . . . . . . . . . . . . . 207 internal snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 l2 cache cache line (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 cache-line replacement. . . . . . . . . . . . . . . . . . . . . . . . . 214 data reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 direct access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 disabling for debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 edx register content . . . . . . . . . . . . . . . . . . . . . . . . . . 265 level-2 cache array access register (l2aar). . . . . . 50 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 rdmsr instruction effect . . . . . . . . . . . . . . . . . . . . . . 265 sector and line organization (figure). . . . . . . . . . . . . . 265 tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . 213 , 264 tag information (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 52 tag or data location (figure) . . . . . . . . . . . . . . . . . . . . . .51 tag reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 wrmsr instruction effect . . . . . . . . . . . . . . . . . . . . . .265 l3 cache debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 pcd signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 level-2 cache array access register (l2aar) . . . . . . . 264 -line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 , 264 -line replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . 214 , 224 masking cache accesses with a20m# . . . . . . . . . . . . . . . 227 mesi states in the data. . . . . . . . . . . . . . . . . . . . . . . . . . . 207 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C 17 , 208 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C 17 , 220 sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . 16 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . . .8 total internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 tr12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 translation lookaside buffers (tlbs). . . . . . . . . . . . . . . . 205 write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 write cycle order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 write to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . 216 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 16 writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 cache# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
index 339 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 capacitor placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 large capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 capture-dr state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 capture-ir state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 measuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 clk switching characteristics 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 298 60-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 299 clk signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 clock control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 , 277 states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 enhanced power management stop grant . . . . . . . . . 277 halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 state transitions (figure) . . . . . . . . . . . . . . . . . . . 278 C 279 stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 , 285 stop grant. . . . . . . . . . . . . . . . . . . . . . . . . . . 193 , 280 , 283 stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 switching characteristics 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 298 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 299 coherency cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 compatibility, floating-point, mmx, and 3dnow! instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 configuration power-on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 signal timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 signal timing for 100-mhz bus operation (table) . . . . . . 308 signal timing for 66-mhz bus operation . . . . . . . . . . . . . 309 vcc pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 connections pin requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 power requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 control register 0 (cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 control register 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 control register 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 control register 3 (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 control register 4 (cr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 counter, time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 cpga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 C 3 pin designations (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 324 pin designations by function (table) . . . . . . . . . . . . . . . . 326 pin differences (table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 cr4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii cycles bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 hold and hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . 168 inquire . . . 94 C 99 , 109 , 113 C 114 , 131 , 139 , 164 , 168 , 170 , . . . . 172 , 174 , 176 C 178 , 182 , 186 , 222 , 263 , 277 , 280 C 282 inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 168 interrupt acknowledge . . . . . . . . 95 , 98 , 100 , 106 , 123 , 138 locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 96 pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 writeback . . . . . . 94 , 96 C 97 , 110 , 113 , 139 , 164 , 172 , 176 , . . . . . . . . . . . . . . . . . . . . . 178 , 180 , 186 , 210 , 264 , 279 , 282 d d/c# signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 d[63:0] signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 data bus ahold restriction . . . . . . . . . . . . . . . . . . . . . . . . 97 , 180 ahold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 aligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 brdy# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 byte enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 d[63:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 data state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 memory reads and writes . . . . . . . . . . . . . . . . . . . . . . .158 misaligned transfers . . . . . . . . . . . . . . . . . . . . . . 129 , 184 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 , 125 split cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 mesi states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 types 3dnow!? technology. . . . . . . . . . . . . . . . . . . . . . . . . . . 37 floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 mmx technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 data/code signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 data-na# requested state. . . . . . . . . . . . . . . . . . . . . . . . . . 156 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 270 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 system management mode (smm) . . . . . . . . . . . . .249 C 250 decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . 294 descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 device identification register (dir) . . . . . . . . . . . . . . . . . 258 diagrams key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 , 311 C 314 waveform definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 digital signal processing instructions . . . . . . . . . . . . . . . . . 90 dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 dissipation, power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii dp[7:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 driven signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 dsp instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 , 239 dual voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
340 index amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information e eads# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 eas register time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . 46 eax register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 bist results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 cache accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ebf field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ebp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ebx register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ecx register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 , 46 edi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 edx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 cache accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 C 51 stepping id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 time stamp counter value . . . . . . . . . . . . . . . . . . . . . . . . . 46 efer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 , 47 , 202 , 229 effective bus frequency divisor field . . . . . . . . . . . . . . . . 150 eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 , 242 eip register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 embedded processor features . . . . . . . . . . . . . . . . . . . . . . . . 1 emms instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 en bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 enhanced power management special bus cycle (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 142 special bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 enhanced power management register (epmr) . . . . . . . 144 epm 16-byte i/o block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 epm stop grant state . . . . . . . . . . . . . . . . . . . . . . . . . 142 , 150 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 voltage identification output state . . . . . . . . . . . . . . . . . 147 epmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 , 144 esi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 esp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ewbe# control (ewbec) . . . . . . . . . . . . . . . . . . . . . . . . . . 229 ewbe# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 , 229 , 280 exception. . . . 98 C 99 , 108 , 125 , 192 , 240 , 249 C 250 , 273 C 275 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 C 33 floating-point. . . . . . . . . . . . . . . . . . 111 , 116 , 237 C 238 , 240 handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 handling floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . 237 machine check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mmx technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 summary (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 system management mode (smm) . . . . . . . . . . . . . . . . . 250 execution latency (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3dnow!? technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 26 execution latency (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 , 21 , 237 multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 23 C 24 , 239 register x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 24 register y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 24 throughput (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 extended feature enable register (efer) . 44 , 47 , 202 , 229 external address strobe signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 write buffer empty signal . . . . . . . . . . . . . . . . . . . . . . . . . 110 extest instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 f femms instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ferr# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 , 238 , 240 float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 , 141 floated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 floating-point and mmx/3dnow! instruction compatibility . . . . . . . . . 240 and multimedia execution units . . . . . . . . . . . . . . . . . . . 237 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 register data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 flush# signal . . . . . . . . . . . . . . . . . .112 , 199 , 223 , 252 , 280 fpu control word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 status word register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 tag word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 , 298 C 299 , 310 control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 105 , 199 g gate descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 62 general-purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 generate special bus cycle bit . . . . . . . . . . . . . . . . . . . . . . 145 global ewbe# disable (gewbed). . . . . . . . . . . . . . . . . . . 230 ground pin designations (table) . . . . . . . . . . . . . . . . . . . . . 327 , 331 plane capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 pulldown resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 split planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 unused active high inputs. . . . . . . . . . . . . . . . . . . . . . . . . 295 gsbc bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 h halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 highz instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 modified line, ahold-initiated inquire. . . . . . . . . . . . . 178 modified line, hold-initiated inquire . . . . . . . . . . . . . . 172 shared or exclusive line, ahold-initiated inquire . . . . 176 shared or exclusive line, hold-initiated inquire . . . . . 170 hit# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 hitm# signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 hlda signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 hold acknowledge cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 acknowledge signal . . . . . . . . . . . . . . . . . . . . . 114 , 168 C 170
index 341 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information hold signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 -initiated inquire hit to modified line. . . . . . . . . . . . . . . 172 -initiated inquire hit to shared or exclusive line . . . . . . 170 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 , 312 i i/o misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . . 167 read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 ibf field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 ieee 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 , 253 ieee 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 , 31 , 237 ieee 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 ignne# signal . . . . . . . . . . . . . . . . . . . . . . . . . . 116 , 238 , 240 ignore numeric exception . . . . . . . . . . . . . . . . . . . . . . . . . . 116 init signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 , 242 , 280 -initiated transition from protected mode to real mode 196 processor state after . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 output signal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 power-on configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 199 processor state after init . . . . . . . . . . . . . . . . . . . . . . . . 203 processor state after reset . . . . . . . . . . . . . . . . . . . . . . 200 register state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 signals sampled during reset . . . . . . . . . . . . . . . . . . . . 199 input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 pin float conditions (table) . . . . . . . . . . . . . . . . . . . . . . . 141 pin types (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 setup and hold timing 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 302 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 306 input/output (i/o), capacitance . . . . . . . . . . . . . . . . . . . . . 290 inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 , 173 , 175 , 277 bus arbitration cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 cycle hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 cycle hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . 113 cycles . . . . . . . . .94 C 99 , 109 , 113 C 114 , 131 , 139 , 164 , 168 , . . . . . . . . . . . 170 , 172 , 174 , 176 C 178 , 180 , 182 , 186 , 222 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 , 277 , 280 C 282 miss, ahold-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3dnow!? technology . . . . . . . . . . . . . . . . . . . . . .89 C 90 , 239 3dnow!? technology (table) . . . . . . . . . . . . . . . . . . . . 89 C 90 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 digital signal processing. . . . . . . . . . . . . . . . . . . . . . . . . . 239 digital signal processing (table) . . . . . . . . . . . . . . . . . . . . 90 emms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 femms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 floating-point (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 integer (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 invd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 mmx technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 , 239 mmx technology (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 86 pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 220 rsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 serializing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 supported by the processor (table) . . . . . . . . . . . . . . . . . . 63 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 wbinvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 integer data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 interrupts . . . . . . . 130 , 188 , 192 , 196 , 237 C 238 , 240 , 242 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 , 274 , 282 01h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 03h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 acknowledge. . . . . . . 95 , 103 , 106 , 118 , 120 , 125 , 184 , 188 acknowledge cycle definition (table) . . . . . . . . . . . . . . . 188 acknowledge cycles . . . . . . . . . . 95 , 98 , 100 , 106 , 123 , 138 clock grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 descriptor table register . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 , 118 , 130 floating-point exceptions . . . . . . . . . . . . . . . . . . . . .237 C 238 gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 init. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 , 242 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 irq13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 mmx instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 , 203 , 242 redirection bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 service routine . . . . . . . . . . . . . . . . . . . . . 118 , 123 , 238 , 241 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 summary (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 type of. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 intr signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 , 280 inv signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 invalidation request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 invd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 iobase field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 k ken# signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 l l1 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 cache line (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 cache-line replacements . . . . . . . . . . . . . . . . . . . . . . . . . . 214 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 , 227 data cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . 207 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 , 211 C 212 flushing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 instruction cache line (figure) . . . . . . . . . . . . . . . . . . . . . 207 internal snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 mesi states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . 16 states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 221 , 225 C 226 write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
342 index amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information l2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 C 113 , 139 , 142 access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 built-in self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 cache line (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 cache sector and line organization (figure) . . . . . . . . . . 265 cache-line fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 cache-line replacements. . . . . . . . . . . . . . . . . . . . . . . . . . 214 coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 data location (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 data reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 direct access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 C 212 disabling for debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 inquire cycles (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 least recently used (lru) algorithm . . . . . . . . . . . . . . . 215 level-2 cache array access register (l2aar). . . . . . . . 50 lru field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 mesi states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 organization (figure). . . . . . . . . . . . . . . . . . . . . . . . . 206 , 265 predecode bits not stored. . . . . . . . . . . . . . . . . . . . . . . . . 208 prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 sector organization (figure) . . . . . . . . . . . . . . . . . . . . . . . . 16 states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . .221 , 225 C 226 super7 platform support . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 t/d bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 , 264 tag information (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 tag location (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 tag reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 l2aar . . . . . . . . . . . . . . . . . . . . . . . 44 , 50 , 212 C 213 , 264 C 267 l3 cache debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 pcd signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 latency, execution (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 layout and airflow considerations . . . . . . . . . . . . . . . . . . 319 level-2 cache array access register (l2aar). . . . . 264 C 267 literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii lock# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 locked cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 operation with boff# intervention . . . . . . . . . . . . . . . . 186 operation, basic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 logic branch-prediction . . . . . . . . . . . . . . . . . . . . . . 15 , 23 , 25 C 26 external support of floating-point exceptions . . . . . . . . 238 symbol (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 low-power devices . . . . . . . . . . . . . . . . . 4 , 288 , 291 C 292 , 336 m m/io# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 machine check address register (mcar) . . . . . .44 C 45 , 202 machine check exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 machine check type register (mctr) . . . . . . . . .44 C 45 , 202 maskable interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 mcar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 C 45 , 202 mctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 C 45 , 202 memory management registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 or i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 read and write, misaligned single-transfer . . . . . . . . . . . 160 read and write, single-transfer. . . . . . . . . . . . . . . . . . . . .158 reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 type range registers (mtrr) . . . . . . . . . . . . . . . . . . 49 , 231 mesi . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 , 168 , 172 , 206 , 227 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 , 207 , 209 states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 207 microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 , 11 C 26 branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 enhanced risc86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 instruction fetching and decode . . . . . . . . . . . . . . . . . . . . 17 instruction prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 misaligned i/o read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 i/o transfers (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 memory transfers (table) . . . . . . . . . . . . . . . . . . . . . . . . . 160 single-transfer memory read and write . . . . . . . . . . . . . . 160 transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 mmx technology . . . . . . . . . . . . . . . . . . . . . . . . 19 , 21 C 24 , 127 3dnow!? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 init state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 instruction compatibility, floating-point and . . . . . . . . . 240 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 instructions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 reset state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . . 44 msr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 mtrr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 , 231 multimedia and 3dnow!? execution units . . . . . . . . . . . . . . . . . . . . .239 execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 239 functional unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 n na# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 negated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 next address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 nmi signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 , 242 , 280 no-connect pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 , 295 non-maskable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 non-pipelined single-transfer memory read/write and write delayed by ewbe#. . . . . . . . . . . . . . . . . . . . .159 normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 o obga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 C 3 pin designations (figure) . . . . . . . . . . . . . . . . . . . . . . . . . 328 pin designations by function (table) . . . . . . . . . . . . . . . . 330 pin differences (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
index 343 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 opn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 ordering part number (opn) . . . . . . . . . . . . . . . . . . . . . . . 335 output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 delay timings 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 300 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 304 leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 pin float conditions (table) . . . . . . . . . . . . . . . . . . . . . . . 141 signal state after reset (table) . . . . . . . . . . . . . . . . . . . 200 p package socket 7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 super7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 packed decimal data register . . . . . . . . . . . . . . . . . . . . . . . 34 page cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 directory entry (pde) . . . . . . . . . . . . . . . . . . . . . .57 C 58 , 209 flush/invalidate register (pfir) . . . . . . . . . . . . . . . . . . . 223 table entry (pte) . . . . . . . . . . . . . . . . . . . . . . . . 57 , 59 , 209 writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 , 100 , 108 , 125 , 158 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 , 108 , 125 check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 C 99 , 108 , 125 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 , 125 , 174 , 255 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 pcd signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 , 209 , 219 generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 pchk# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 pfir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 C 50 , 202 , 223 pins connection requirements . . . . . . . . . . . . . . . . . . . . . . . . . 295 designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 C 331 float conditions (table). . . . . . . . . . . . . . . . . . . . . . . . . . . 141 i/o voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 input pin types (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 logic symbol (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 no-connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 C 139 pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 C 157 , 162 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 C 25 data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 register x and y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pipelined . . . . . . . . . . . . . . . .23 , 122 , 157 , 162 C 163 , 180 , 220 burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 96 , 107 design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 platform socket 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 super7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pointer, instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 consumption and thermal resistance (figure) . . . . . . . . 317 dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 isolation region between planes . . . . . . . . . . . . . . . . . . . 293 management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 management, enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . 143 plane capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 powernow! technology. see amd powernow!? technology. power-on configuration and initialization . . . . . . . . . . . . . 199 precision real data registers . . . . . . . . . . . . . . . . . . . . . . . . 34 predecode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 C 17 , 208 prefetch instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 prefetch instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 220 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 processor absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 amd powernow!? technology. . . . . . . . . . . . . . . . . . . . .143 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 cache organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 , 205 clock control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 logic symbol (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 low-power devices . . . . . . . . . . . . . . . . . . 288 , 291 C 292 , 336 microarchitecture overview . . . . . . . . . . . . . . . . . . . . . . . . 11 multimedia execution unit . . . . . . . . . . . . . . . . . . . . . . . . 239 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 pin connection requirements . . . . . . . . . . . . . . . . . . . . . .295 power-on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 process technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 signal switching characteristics . . . . . . . . . . . . . . . . . . . . 297 socket 7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 standard-power devices. . . . . . . . . . . . . . . . . . . . . . 288 , 336 state observability register (psor). . . . . . . . . . . . . 49 , 202 super7 platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 system management mode (smm) . . . . . . . . . . . . . . . . . 241 test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 processor state observability register (psor) low-power version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 protected mode init-initiated transition . . . . . . . . . . . . . . . . . . . . . . . . . . 196 real mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 psor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 , 148 , 202 pwt signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 generation (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 r rdmsr instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 rdtsc instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 read and write basic i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 misaligned i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 reads, burst reads and pipelined burst . . . . . . . . . . . . . . 162
344 index amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information real mode init-initiated transition . . . . . . . . . . . . . . . . . . . . . . . . . . 196 protected mode transition . . . . . . . . . . . . . . . . . . . . . . . . 196 register x and y functional unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 , 27 , 240 3dnow!? technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 boundary scan (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 bypass (br) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 control 0 (cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 control 1 (cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 control 2 (cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 control 3 (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 control 4 (cr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 data types, floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 34 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 , 270 descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 device identification (dir) . . . . . . . . . . . . . . . . . . . . . . . 258 dr3Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 dr5Cdr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 dr6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 dr7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 eax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ebp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ebx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ecx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 edi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 edx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 eflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 enhanced power management (epmr) . . . . . . . . . . . . . 144 epmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 esi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 esp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 extended feature enable (efer) . . . . . . . 44 , 47 , 202 , 229 floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 fpu control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 fpu status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 fpu tag word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 instruction (ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 level-2 cache array access (l2aar) . . . . . . . . . . . . . . . . 264 machine check address (mcar) . . . . . . . . . . . . .44 C 45 , 202 machine check type (mctr) . . . . . . . . . . . . . . . .44 C 45 , 202 mcar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 memory type range (mtrr) . . . . . . . . . . . . . . . . . . . . . . 231 mmx technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 model-specific (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 packed decimal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 pfir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 precision real data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 processor state observability (psor) . . . . . . . . . . . . . . . 148 processor state observability register (psor) . . . . . 49 , 202 psor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 , 148 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 segment (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 syscall/sysret target address (star) . . . 44 , 48 , 202 system management mode (smm) initial state (table) 243 test (tr12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . 46 tr12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 uwccr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 x and y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 C 22 , 24 regulator, voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 reserved (rsvd) pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 pin designations (table) . . . . . . . . . . . . . . . . . . . . . 327 , 331 reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 , 200 , 280 signals sampled during reset . . . . . . . . . . . . . . . . . . . . . . 199 state of processor after reset . . . . . . . . . . . . . . . . . . . . . . 200 timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 timing for 100-mhz bus operation . . . . . . . . . . . . . . . . . . 308 timing for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . 309 return address stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 risc86 microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 rsm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 , 249 rsvd pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 s sample/preload instruction . . . . . . . . . . . . . . . . . . . . . 260 sampled signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 scheduler/instruction control unit . . . . . . . . . . . . . . . . 14 , 21 scyc signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 sector, write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 , 220 segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 59 C 61 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 task state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 segment registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 serializing instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 sgtc field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 , 283 shift-dr state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 shift-ir state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 signals a[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 a20m#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 , 242 ads# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 adsc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ahold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 , 280 ap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 apchk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 be[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 bf[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 , 285 boff#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 , 182 brdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 brdyc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 breq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 cache# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 , 210 cache-related . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 d/c# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 d[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 C 139 dp[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 eads# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ewbe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 , 229 , 280 ferr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 , 240 floated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 flush# . . . . . . . . . . . . . 112 , 199 , 223 , 252 , 280 , 283 C 284 hit# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
index 345 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information hitm# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 hlda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ignne# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 , 240 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 , 280 , 283 intr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 , 280 , 283 inv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ken# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 lock# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 logic symbol (figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 m/io# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 na#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 negated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 nmi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 , 280 , 283 output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 pchk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 pwt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 , 280 , 283 rsvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 sampled during reset . . . . . . . . . . . . . . . . . . . . . . . . . . 199 scyc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 , 241 , 280 , 283 smiact# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 , 241 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 , 280 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 297 tck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 tdi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 tdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 timing (figures) . . . . . . . . . . . . . . . . . . . . .159 C 197 , 311 C 314 tms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 vcc2det . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 vcc2h/l# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 vid[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 , 151 w/r#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 wb/wt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 simd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 single instruction multiple data (simd) operations . . . . . 15 single-transfer memory read and write. . . . . . . . . . . . . . 158 smi# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 , 241 , 280 smiact# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 , 241 smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 , 139 , 164 cache states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 instruction cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 internal cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 processor-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 exceptions (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 instructions supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 interrupts (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 memory management registers . . . . . . . . . . . . . . . . . . . . . 54 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . 44 paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 software prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 special bus cycles brdy# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 cache invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 cache writeback invalidation . . . . . . . . . . . . . . . . . . . . . .190 definition (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 differentiating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 , 190 encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 , 190 enhanced power management . . . . . . . . . . . . . . . . . . . . . 145 epm stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 ewbe# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 flush acknowledge . . . . . . . . . . . . . . . . . . 112 , 164 , 190 , 212 halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 C 191 , 280 shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 , 192 signal states (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 stop grant . . . . . . . . . . . . . . . . . . . . . . . . . 132 , 190 , 193 , 281 system management mode (smm) . . . . . . . . . . . . . . . . . 247 speculative ewbe# disable (sewbed). . . . . . . . . . . . . . . 230 split cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 standard-power devices . . . . . . . . . . . . . . . . . . . . . 4 , 288 , 336 star . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 , 48 , 202 state bus machine (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 processor after init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 after reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 stepping id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . .291 C 292 clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 , 285 grant inquire state. . . . . . . . . . . . . . . . . . . . . . . . . 277 , 280 C 282 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 , 280 , 282 grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 stop grant time-out counter field . . . . . . . . . . . . . . . . . . 150 storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 stpclk# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 , 280 super7 platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 input setup and hold timings for 100-mhz bus. . . . . . . . 302 input setup and hold timings for 66-mhz bus. . . . . . . . . 306 output delay timings for 100-mhz bus . . . . . . . . . . . . . . 300 output delay timings for 66-mhz bus . . . . . . . . . . . . . . . 304 signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 valid delay, float, setup, and hold timings . . . . . . . . . . .300 syscall instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 syscall/sysret target address register (star) . 44 , 48 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 sysret instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 system management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 management interrupt active. . . . . . . . . . . . . . . . . . . . . .131 system design airflow management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 atx form factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 component placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 decoupling recommendations . . . . . . . . . . . . . . . . . . . . . 294 heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 pin connection requirements . . . . . . . . . . . . . . . . . . . . . .295 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
346 index amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information system management mode (smm) . . . . . . . . . . . . . . . . . . . 241 amd powernow!? features . . . . . . . . . . . . . . . . . . . . . . 145 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 debugging in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 default register values . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 enhanced power management . . . . . . . . . . . . . . . . . . . . . 145 entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 exceptions in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 i/o trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 initial register state (table) . . . . . . . . . . . . . . . . . . . . . . . 243 interrupts in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 memory (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 nmi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 rsm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 smi# interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 smiact# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 state-save area (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 system management interrupt active signal . . . . . . . . . 131 system management interrupt signal . . . . . . . . . . . . . . . 130 t tap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 task state segment (tss) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 tck signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 tdi signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 tdo signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 technical publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 , 315 , 317 ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 case-to-ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 extended for low-power devices . . . . . . . . . . . . . . . . . . . 315 storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 terminology, signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 test boundary-scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 built-in self-test (bist). . . . . . . . . . . . . . . . . . . . . . . . . . . 251 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 data input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 data output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 l2 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 -logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 register 12 (tr12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 scan chain (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 signal timing (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 signal timing (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 tag array testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 test access port (tap). . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 three-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 test access port (tap) instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 highz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 sample/preload . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 boundary scan (bsr). . . . . . . . . . . . . . . . . . . . . . . . . . . 255 bypass (br) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 device identification (dir) . . . . . . . . . . . . . . . . . . . . . 258 instruction register (ir) . . . . . . . . . . . . . . . . . . . . . . . . 255 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 states capture-dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 capture-ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 shift-dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 shift-ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 update-dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 update-ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 , 320 C 321 design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 extended temperature rating . . . . . . . . . . . . . . . . . . . . . .315 heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 layout and airflow consideration . . . . . . . . . . . . . . . . . . . 319 measuring case temperature (figure) . . . . . . . . . . . . . . . 319 model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 third-party support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv three-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 time stamp counter register (tsc). . . . . . . . . . . . . . . . . . . 46 timing bus cycles (figures) . . . . . . . . . . . . . . . . . . . . . . . . . .159 C 197 switching characteristics (figures) . . . . . . . . . . . . . .311 C 314 tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 tms signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 tr12 . . . . . . . . . . . . . . . . . . . . . . . . 44 , 46 , 202 , 210 , 218 , 263 transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 translation lookaside buffer (tlb) . . . . . . . . . . . . . . . . . . 205 trst# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 tsc . . . . . . . . . . . . . . . . . . . . . . . . . .44 , 46 , 202 , 280 C 281 , 283 tss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 , 61 C 62 , 244 , 273 u uc memory type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 uc/wc cacheability control register (uwccr) . . 200 , 202 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 uncacheable memory . . . . . . . . . . . . . . . . . . . . . . 49 , 230 C 231 uwccr . . . . . . . . . . . . . . . . . . . . . . . . . 49 , 200 , 202 , 210 , 232 v vcc2 pins absolute ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 pin designations (table) . . . . . . . . . . . . . . . . . . . . . 327 , 331 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 processor voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 vcc2det signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 vcc2h/l# signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 vcc3 pins absolute ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 i/o voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 pin designations (table) . . . . . . . . . . . . . . . . . . . . . 327 , 331
index 347 23543a/0september 2000 amd-k6?- iii e+ embedded processor data sheet preliminary information power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 unused active low inputs . . . . . . . . . . . . . . . . . . . . . . . . . 295 vid[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 , 151 vid[4:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 vidc bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 vido field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 voltage active high signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 active low signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 bus divisor (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 clk switching characteristics . . . . . . . . . . . . . . . . . . . . . 298 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 dual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 , 293 input low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 plane isolation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 C 320 supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 vcc2 detect signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 vcc2 high/low signal. . . . . . . . . . . . . . . . . . . . . . . . . . . 136 vcc2det signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 voltage identification control (table) . . . . . . . . . . . . . . . 147 vss pins connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 pin designations (table) . . . . . . . . . . . . . . . . . . . . . . 327 , 331 unused active high inputs . . . . . . . . . . . . . . . . . . . . . . . . 295 w w/r# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 wb/wt# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 wbinvd instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 wc memory type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 whcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 , 48 , 202 , 219 write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . 208 , 215 C 216 , 219 conditions (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 logic mechanisms and conditions (figure) . . . . . . . . . 219 handling control register (whcr) . . . . . . . . . . . . . 202 , 219 to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 , 220 write merge buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 ewbe# control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 ewbec settings (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 231 memory type range registers (mtrrs) . . . . . . . . . . . . . 231 memory-range restrictions . . . . . . . . . . . . . . . . . . . . . . . . 233 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 valid masks and range sizes (table) . . . . . . . . . . . . . . 234 performance (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 uc/wc cacheability control register (uwccr). . . . . 232 uncacheable memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 write cycle order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 write-combining memory . . . . . . . . . . . . . . . . . . . . . . . . . 231 write/read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 writeback . . . . . . . . . 105 , 107 C 108 , 119 , 126 , 131 , 139 , 142 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 C 165 , 190 , 278 burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 16 coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 cycles . . . . . . . . . 94 , 96 C 97 , 110 , 113 , 139 , 164 , 172 , 176 , . . . . . . . . . . . . . . . . . 178 , 180 , 182 , 186 , 210 , 264 , 279 , 282 l1 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 l2 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 or writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 write-combining memory . . . . . . . . . . . . . . . . . . 49 , 230 C 231 writethrough coherency state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 memory writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
348 index amd-k6?- iii e+ embedded processor data sheet 23543a/0september 2000 preliminary information

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